2nd 3rd 4th, Beat | Motorola MVME2300 Series guide

Functional Description

Table 3-2. PowerPC 60x Bus to DRAM Access Timing — 70ns Page Devices

		Clock Periods Required For:					Total
Access Type
	1st		2nd	3rd		4th
							Clocks
							Clocks
	Beat		Beat	Beat		Beat

4-Beat Read after Idle (Quad-	10		1	3		1	15
word aligned)

4-Beat Read after Idle (Quad-	10		4	1		1	16
word misaligned)

4-Beat Read after 4-Beat Read	9/3 1		1	3		1	14/8
(Quad-word aligned)

4-Beat Read after 4-Beat Read	7/2 1		4	1		1	13/8
(misaligned)

4-Beat Write after Idle	4		1	1		1	7
	4		1	1		1
4-Beat Write after 4-Beat Write	10/6 1		1	1		1	13/9
(Quad-word aligned)

1-Beat Read after Idle	10		-	-		-	10
	10		-	-		-
1-Beat Read after 1-Beat Read	11/7 1		-	-		-	11/7
1-Beat Write after Idle	4		-	-		-	4
	4			-		-
1-Beat Write after 1-Beat Write	1		-	-		-	15/11
1-Beat Write after 1-Beat Write	15/11		-	-		-	15/11
	15/11

Notes

1.These numbers assume that the PowerPC 60x bus master is doing address pipelining with TS_ occurring at the minimum time after AACK_ is asserted. Also, the two numbers shown in the 1st Beat column are for page miss/page hit.

2.In some cases, the numbers shown are averages and specific instances may be longer or shorter.

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Motorola MVME2300 Series manual PowerPC 60x Bus to Dram Access Timing 70ns Page Devices, 2nd 3rd 4th, Beat

Contents

MVME2300 Series VME Processor Module Programmer’s Reference GuidePage Safety Summary Instructions Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Raven PCI Bridge Asic Page Page Falcon ECC Memory Controller Chip Set Universe VMEbus to PCI Chip Chapter Page List of Figures Page List of Tables Xviii 16MB ECC Dram Model Memory Processor32MB ECC Dram 64MB ECC Dram Date Description of Change Summary of Changes Comments and Suggestions Overview of Contents Bold Conventions Used in This ManualEnter, Return or CR Ctrl Xxiii Xxiv Overview Introduction Features MVME2300 Series Summary of FeaturesFeature MVME2300 ECC Dram Scsa I/O System Block Diagram Board Description and Memory Maps MVME2300 Series System Block Diagram VMEbus Interface Functional DescriptionFront Panel PCI interface Programming ModelProcessor Memory Maps P2 I/O Processor Address Size Definition Start End Default Processor Memory Map Chrp Memory Map Example Processor Chrp Memory Map Address Register Name Register Value Raven MPC Register Values for Chrp Memory Map Prep Memory Map Example Processor Prep Memory MapBfff Ffff Raven MPC Register Values for Prep Memory Map PCI Configuration Access PCI Memory Maps Default PCI Memory MapPCI Chrp Memory Map PCI Address Size Definition Start End FC03 Ffff Raven PCI Register Values for Chrp Memory Map Configuration Register Value Address Offset Register NameUniverse PCI Register Values for Chrp Memory Map 10. PCI Prep Memory Map PCI Prep Memory Map 39FE Ffff 38FF Ffff39FF Ffff 3AFE Ffff 11. Raven PCI Register Values for Prep Memory Map 12. Universe PCI Register Values for Prep Memory Map VMEbus Master Map VMEbus Mapping VMEbus Slave Map VMEbus Slave Mapping VSI0BS VSI0CTLVSI0BD VSI0TO Falcon-Controlled System Registers VMEbus Address Size Chrp Map Prep Map Range Mode14. VMEbus Slave Map Example 15. System Register Summary System Configuration Register $FEF80400 System Configuration Register Syscr$FD Sysclk Value System Clock Speed PCI Clock Speed P0/1STAT Value Processor 0/1 Present External In-line Cache Memory Configuration Register $FEF80404 Memory Configuration Register MemcrMSIZE01 MSIZE01 Total Memory On Board RA/BTYP02 MSPD01L2TYPE03 FLSHP02 L2PLL03System External Cache Control Register Sxccr PLL Value Size Processor 1 External Cache Control Register P1XCCR Processor 0 External Cache Control Register P0XCCRCPU Control Register CPU Control Register $FEF88300 ISA Local Resource Bus Access RegistersW83C553 PIB Registers Uart General-Purpose Readable Jumpers NVRAM/RTC and Watchdog Timer Registers 17. M48T59/559 Access Registers Module Configuration and Status Registers18. Module Configuration and Status Registers PCI I/O Address Function Old CPU Configuration Register $FE000800 CPU Configuration RegisterCputype SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Base Module Feature Register Offset $0802 Base Module Feature RegisterPcixp PMC2P PMC1P Vmep Lanp Basetype Base Module Status Register BmsrBase Module Status Register Offset $0803 Basetype Seven-Segment Display Register VME RegistersSegment Display Register Offset $08C0 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 LM/SIG Control Register 19. VME RegistersSETSIG1 SETSIG0 LM/SIG Status Register Board Description and Memory Maps Location Monitor Lower Base Address Register Location Monitor Upper Base Address RegisterLocation Monitor Upper Base Address Register Offset $1002 Location Monitor Lower Base Address Register Offset $1003 Semaphore Register 1 Offset $1004 Semaphore RegisterSEM1 Semaphore Register 2 Offset $1005 20. Emulated Z8536 Access Registers Emulated Z8536 CIO Registers and Port PinsVME Geographical Address Register Vgar Emulated Z8536 Registers Port Signal Direction Descriptions Pin Name Z8536 CIO Port Pins21. Z8536 CIO Port Pin Assignments PC2 BASETYP0 ISA DMA ChannelsPC3 BASETYP1 Page Features of the Raven Asic FeaturesFunction Features Block Diagram Raven Block Diagram MPC Address Mapping MPC Bus Interface MPC-to-PCI Address Decoding MPC Slave MPC to PCI Address Translation MPC Transfer Type Transaction Encoding Command Types MPC Slave Response MPC Master MPC Write Posting MPC Transfer Types PCI Command CodeMPC Transfer Type MPC Transfer Size TT0-TT4 MPC Arbiter MPC Bus Timer PCI Address Mapping Configuration Registers PCI to MPC Address Decoding MPC Bus Address Space Decoder Priority RavenMPIC Control Registers PCI Slave Command Types PCI Slave Response Command TypesCommand Type Slave Response? Addressing Device Selection Exclusive AccessTarget-Initiated Termination Fast Back-to-Back Transactions Cache Support ParityPCI Write Posting PCI Master PCI Command PCI Master Command CodesEntity Addressed Transfer Type Master Initiated Termination Combining, Merging, and Collapsing Arbitration Latency ArbitrationAddress/Data Stepping Generating PCI Memory and I/O Cycles Generating PCI CyclesPCI Cycle Type PCI Spread I/O Address Translation Generating PCI Configuration Cycles Functional Description Device Number Address Bit Generating PCI Special Cycles Endian Conversion When MPC Devices are Big-EndianGenerating PCI Interrupt Acknowledge Cycles Big- to Little-Endian Data Swap Raven Registers and Endian Mode When MPC Devices are Little-EndianAddress Modification for Little-Endian Transfers Data Address Length Bytes Modification Error Handling Transaction Ordering Error Status Error Address AttributesSMA Perr MPC Registers Raven Registers Raven MPC Register Map Venid Vendor ID/Device ID RegistersDevid Revision ID Register General Control-Status/Feature RegistersRevid Revision ID. Identifies the Raven revision level. This Bhog FlbrdMarb Mpic Feat MIDxCurrent MPC Data Bus Master Operation Reset $00 Prescaler Adjust RegisterOperation Reset $00 $B4 MPC Arbiter Control Register Matom MPC Error Enable Register Rtam SmamMatoi Perri OVF MPC Error Status RegisterMato SMA Writing it to a 0 has no effect. When the Smam bitPCI transaction. The bit may be cleared by writing it to a RTA Which originated the transfer in which the error occurred MPC Error Attribute Register MeratRegister TTx Designates a selected byte PCI Interrupt Acknowledge Register Operation Reset $0000Piack Address $FEFF0030 Bit Name Start Operation Reset $8000 $8080END MPC Slave Address 3 Register MSOFFx MPC Slave Offset/Attribute 0,1 and 2 RegistersREN WEN IOM WpenMSOFF3 PCI Registers Cycles. When clear, the corresponding MPC slave will $0C Raven PCI Configuration Register Map$18 $7F $8C Raven PCI I/O Register Map Operation Reset $4801 $1057$CF8 Offset $00 Bit Name PCI Command/ Status Registers Seltim DparSigta Rcvta Class Revision ID/ Class Code RegistersBase Register Space Ioba RESIO/MEM PRE PCI Slave Address 0,1,2 and 3 Registers To access MPC bus resources. The value of this field willBe compared with the upper 16 bits of the incoming PCI INV PCI Slave Attribute/ Offset 0,1,2 and 3 RegistersTransfer type code which specifies the current transaction GBL Perspective from the MPC bus in Big-Endian mode Configaddress RegisterConceptual perspective from the PCI bus REG Perspective from the MPC bus in Little-Endian modeFUN DEV Configdata Register EN EnableBUS Data ‘B’ Data ‘C’ Data ‘D’ Operation Reset Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation Reset Raven Interrupt Controller FeaturesArchitecture Interrupt Source Priority Readability of CSRProcessor’s Current Task Priority Spurious Vector Generation Nesting of Interrupt EventsInterprocessor Interrupts IPI Compatibility Timers Raven-Detected Errors Interrupt Delivery Modes Raven Interrupt Controller Block Diagram Description Interrupt Pending Register IPR Program-Visible RegistersInterrupt Selector is Interrupt Request Register IRR In-Service Register ISRInterrupt Router Raven PCI Bridge Asic RavenMPIC Registers Mpic Registers10. RavenMPIC Register Map Off $010F0 $010E0$011E0 $100F0 $100E0 $101F0 $101E0 Ncpu Feature Reporting RegisterVID Offset $01020 Bit Name Global Configuration Register Vendor Identification Register Processor 1. Writing a 1 to P1 will assert the Soft ResetSTP Processor Init Register Mask IPI Vector/Priority RegistersACT Prior Interrupt Acknowledge register is read during a spurious Spurious Vector RegisterVector fetch Offset $010E0 Bit Name Timer Base Count Registers Timer Current Count Registers This timer. Setting the bit to 0 allows counting to proceed Count Inhibit. Setting this bit to 1 inhibits counting forBase Count. This field contains the 31-bit count for this Bit transitions from a 1 to a 0, the value is copied into Timer Destination Registers External Source Vector/Priority Registers Setting this bit to a 0 enables active low or negative edgePOL Sense External Source Destination Registers Offset $10200 Bit Name Raven-Detected Errors Vector/Priority Register Offset $10210 Bit Name Raven-Detected Errors Destination Register Offset Processor $20080 $21080 Bit Name Interrupt Acknowledge Registers Zero is assumed. Writing to this register signals the endEnd-of-Interrupt Registers End Of Interrupt. There is one EOI register per Programming Notes External Interrupt Service Reset State Interprocessor Interrupts Dynamically Changing I/O Interrupt Configuration Interrupt Acknowledge Register EOI RegisterMode Current Task Priority Level Architectural Notes Page Dram Features of the Falcon Chip Set Falcon Pair Used with Dram in a System Block Diagrams Falcon Internal Data Paths Simplified Overall Dram Connections Performance Bit Ordering ConventionFour-beat Reads/Writes Dram Speeds Single-beat Reads/Writes Clock Periods Required For Total Access Type PowerPC 60x Bus to Dram Access Timing 70ns Page Devices2nd 3rd 4th Beat 2nd 3rd 4th Clocks Beat PowerPC 60x Bus to Dram Access Timing 60ns Page Devices PowerPC Bus to Dram Access Timing 50ns Hyper Devices ROM/Flash Speeds Responding to Address Transfers PowerPC 60x Bus InterfaceCompleting Data Transfers Cache Coherency L2 Cache Support Cache Coherency RestrictionsCycle Types Single-Bit Error Reporting Dram Tester Error LoggingROM/Flash Interface Functional Description $XXFFFFF9 $7FFFFD $XXFFFFF8 $7FFFFC$XXFFFFFA $7FFFFE $XXFFFFFB $7FFFFF $X3FFFFF1 $7FFFFE $X3FFFFF0 $7FFFFE$X3FFFFF2 $7FFFFE $X3FFFFF3 $7FFFFE Blocks a and/or B Present, Blocks C and D Not Present Refresh/Scrub Blocks a and/or B Present, Blocks C and/or D Present Dram Arbitration Chip Defaults External Register Set CSR AccessesCSR Architecture Data Path for Reads from the Falcon Internal CSRs Data Path for Writes to the Falcon Internal CSRs Memory Map for Byte Reads to CSR 1906 Memory Map for 4-Byte Reads to CSR Detailed Register Bit Descriptions Register Summary 10. Register Summary Test D3 Lower 32 Bits Programming Model Address $FEF80000 Bit Name Vendor/Device Register Read Zero Read only Revision ID/ General Control Register 11. ram spd1,ram spd0 and Dram Type Ram spd0,ram spd1Ram spd0, ram spd1 Dram Speed Dram Type Ram a/b/c/d en Dram Attributes RegisterRam a/b/c/d siz0-2 Ram a/b/c/d Block Size Devices Used Technology Comments BlockA/B/C/D Configurations0MB SIMM/DIMM RAM A/B/C/D Base Dram Base RegisterCLK Frequency Register CLK Frequency Refdis ECC Control RegisterRwcb Read Zero 11707.00 Falcon ECC Memory Controller Chip Set Sien TienMien Mcken Elog Embt Esen Address $FEF80038 Bit Name Error Address Register 13. rtest Encodings Rtest0,rtest1,rtest2 Test Mode selected Address $FEF80048 Bit Name Refresh/Scrub Address Register 1Mbyte of Block a also appears at $FFF00000 ROM a Base 15. romarv and rombrv Encoding 14. ROM Block a Size EncodingRom a siz Block Size 1MB Cycle Transfer Alignment Romx64 Romxwe Falcon Response 16. Read/Write to ROM/Flash ROM B Base ROM B Base/Size Register1Mbyte of Block B also appears at $FFF00000 Rom b siz Block Size 17. ROM Block B Size Encoding Bit Counter Dram Tester Control RegistersCTR32 is a 32-bit, free-running counter that increments Has been programmed properly. Notice that CTR32 is Address $FEF80400 Bit Name Power-Up Reset Status RegisterAddress $FEF80500 Bit Name Address $FEF88000 $FEF8FFF8 Bit Name External Register Set Software Considerations Parity Checking on the PowerPC BusProgramming ROM/Flash Devices Writing to the Control Registers Sizing Dram Software Considerations 18. Sizing Addresses 19. PowerPC 60x Address to Dram Address Mappings1024MB 256MB 128MB 64MB 32MB 16MB ROW ECC Codes 20. Syndrome Codes Ordered by Bit in ErrorBit Syndrome 20. Syndrome Codes Ordered by Bit in Error $AF $CF $EF 21. Single-Bit Errors Ordered by Syndrome Code Data Paths 10. PowerPC Data to Dram Data Correspondence 22. PowerPC Data to Dram Data Mapping Page Universe VMEbus to PCI Chip − BLT, ADOH, RMW, Lock Features of the Universe Asic Block Diagram Universe as VMEbus Slave Architectural Diagram for the Universe Universe as VMEbus Master PCI Bus Interface Universe as PCI Slave Universe as PCI Master Interrupter VMEbus Interrupt Handling DMA Controller Universe Control and Status Registers Ucsr Ucsr Access Mechanisms Universe Register Map Offset Register Name LSI2BD LSI2BSLSI2TO LSI3BS Dgcs DcppDllue Linten VSI1BS F1C VSI0BD F0CVSI2CTL F2C VSI2BS Description Universe Chip Problems after PCI Reset Method Workarounds Examples Example 1 MVME2600 Series Board Exhibits PCI Reset Problem Example 2 MVME3600 Series Board Acts Differently Run the init code and the LSI0 registers become Example 3 Universe Chip is Checked at Tundra Universe VMEbus to PCI Chip PCI Arbitration Assignments PCI ArbitrationPci Bus Request PCI Masters PIB MVME2300 Series Interrupt Architecture Interrupt Handling RavenMPIC Interrupt Assignments RavenMPICEdge Polarity Interrupt Source Level IRQ14 InterruptsIRQ15 PIB Interrupt Handler Block Diagram Edge PIB PCI/ISA Interrupt Assignments ISA DMA Channels Reset switch Sources of ResetExceptions Reset Sources and Devices Affected Soft ResetSources of Reset Devices Affected Error Notification and Handling Error Notification and HandlingCause Action Big-Endian Mode Endian Issues Little-Endian Mode Role of the Raven Asic Processor/Memory DomainPCI Domain PCI/Ethernet VMEbus Domain Role of the Universe AsicPCI-Graphics Default Mapping for FFF00000-FFFFFFFF ROM/Flash Bank DefaultROM/Flash Initialization Page Document Title Publication Number Motorola Computer Group Documents Document Title and Source Publication Number Manufacturers’ Documents EK-DE500-OM MPCFPE/AD ANSI/IEEE Related SpecificationsIEC 821 BUS Isbn MPR-PPC-RPU-02TIA/EIA-232 Page Glossary O S S a R Y Enhanced Integrated Drive Electronics. An improved version PCI. Used in the reference platform specification. IBM IBM Computers developed by the IBM Corporation. PowerPC is Signal Computing System Architecture. a hardware model for See 10base-2 Page Index PCI 1-13 processor IN-3 PCI MPC IN-5 Configaddress 2-56CONFIGDATA IN-7 IN-8