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Motorola MVME2300 Series manual Prior, Timer Destination Registers

Models: MVME2300 Series

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Raven PCI Bridge ASIC

PRIOR	Interrupt Priority. Priority 0 is the lowest and 15 is the
	highest. Note that a priority level of 0 will not enable
	interrupts.
VECTOR	Interrupt Vector. This vector is returned when the
	Interrupt Acknowledge register is examined upon
	acknowledgment of the interrupt associated with this
	vector.

Timer Destination Registers

Offset															Timer 0 - $01130
															Timer 1 - $01170
															Timer 2 - $011B0
															Timer 3 - $011F0

Bit	3	3	2	2		2	2	2	2	2	2	2	2		1	1	1	1	1	1	1		1		1	1
	1	0	9	8		7	6	5	4	3	2	1	0		9	8	7	6	5	4	3		2		1	0	9	8	7	6	5		4	3	2	1	0

Name													TIMER DESTINATION

																																				P1	P0

Operation				R									R										R								R					R/W	R/W
																																				R/W	R/W

Reset				$00									$00										$00								$00					0	0

This register indicates the destinations for this timer’s interrupts. Timer interrupts operate in the Directed delivery interrupt mode. This register may specify multiple destinations (multicast delivery).

P1	PROCESSOR 1. The interrupt is directed to processor 1.
P0	PROCESSOR 0. The interrupt is directed to processor 0.

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Motorola MVME2300 Series manual Prior, Timer Destination Registers

Contents

Programmer’s Reference Guide MVME2300 Series VME Processor ModulePage Safety Summary Flammability InstructionsCE Notice European Community Limited and Restricted Rights Legend Contents Raven PCI Bridge Asic Page Page Falcon ECC Memory Controller Chip Set Universe VMEbus to PCI Chip Chapter Page List of Figures Page List of Tables Xviii 32MB ECC Dram Model Memory Processor16MB ECC Dram 64MB ECC DramSummary of Changes Date Description of ChangeOverview of Contents Comments and SuggestionsEnter, Return or CR Conventions Used in This ManualBold CtrlXxiii Xxiv Introduction OverviewFeature MVME2300 Summary of FeaturesFeatures MVME2300 Series ECC DramSystem Block Diagram Scsa I/OBoard Description and Memory Maps MVME2300 Series System Block Diagram Functional Description VMEbus InterfaceFront Panel Processor Memory Maps Programming ModelPCI interface P2 I/ODefault Processor Memory Map Processor Address Size Definition Start EndProcessor Chrp Memory Map Chrp Memory Map ExampleRaven MPC Register Values for Chrp Memory Map Address Register Name Register ValueProcessor Prep Memory Map Prep Memory Map ExampleBfff Ffff PCI Configuration Access Raven MPC Register Values for Prep Memory MapPCI Chrp Memory Map Default PCI Memory MapPCI Memory Maps PCI Address Size Definition Start EndFC03 Ffff Configuration Register Value Address Offset Register Name Raven PCI Register Values for Chrp Memory MapUniverse PCI Register Values for Chrp Memory Map PCI Prep Memory Map 10. PCI Prep Memory Map39FF Ffff 38FF Ffff39FE Ffff 3AFE Ffff11. Raven PCI Register Values for Prep Memory Map 12. Universe PCI Register Values for Prep Memory Map VMEbus Mapping VMEbus Master MapVMEbus Slave Map VMEbus Slave Mapping VSI0BD VSI0CTLVSI0BS VSI0TO14. VMEbus Slave Map Example VMEbus Address Size Chrp Map Prep Map Range ModeFalcon-Controlled System Registers 15. System Register Summary$FD System Configuration Register SyscrSystem Configuration Register $FEF80400 Sysclk Value System Clock Speed PCI Clock SpeedP0/1STAT Value Processor 0/1 Present External In-line Cache MSIZE01 Memory Configuration Register MemcrMemory Configuration Register $FEF80404 MSIZE01 Total Memory On BoardMSPD01 RA/BTYP02L2TYPE03 System External Cache Control Register Sxccr L2PLL03FLSHP02 PLL Value SizeCPU Control Register Processor 0 External Cache Control Register P0XCCRProcessor 1 External Cache Control Register P1XCCR CPU Control Register $FEF88300W83C553 PIB Registers Access RegistersISA Local Resource Bus UartNVRAM/RTC and Watchdog Timer Registers General-Purpose Readable Jumpers18. Module Configuration and Status Registers Module Configuration and Status Registers17. M48T59/559 Access Registers PCI I/O Address FunctionCputype CPU Configuration RegisterOld CPU Configuration Register $FE000800 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0Base Module Feature Register Base Module Feature Register Offset $0802Pcixp PMC2P PMC1P Vmep Lanp Base Module Status Register Offset $0803 Base Module Status Register BmsrBasetype BasetypeSegment Display Register Offset $08C0 VME RegistersSeven-Segment Display Register SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0SETSIG1 19. VME RegistersLM/SIG Control Register SETSIG0LM/SIG Status Register Board Description and Memory Maps Location Monitor Upper Base Address Register Offset $1002 Location Monitor Upper Base Address RegisterLocation Monitor Lower Base Address Register Location Monitor Lower Base Address Register Offset $1003SEM1 Semaphore RegisterSemaphore Register 1 Offset $1004 Semaphore Register 2 Offset $1005VME Geographical Address Register Vgar Emulated Z8536 CIO Registers and Port Pins20. Emulated Z8536 Access Registers Emulated Z8536 RegistersZ8536 CIO Port Pins Port Signal Direction Descriptions Pin Name21. Z8536 CIO Port Pin Assignments ISA DMA Channels PC2 BASETYP0PC3 BASETYP1 Page Features Features of the Raven AsicFunction Features Block Diagram Raven Block Diagram MPC Bus Interface MPC Address MappingMPC-to-PCI Address Decoding MPC to PCI Address Translation MPC SlaveCommand Types MPC Slave Response MPC Transfer Type Transaction EncodingMPC Write Posting MPC MasterPCI Command Code MPC Transfer TypesMPC Transfer Type MPC Transfer Size TT0-TT4 MPC Bus Timer MPC ArbiterConfiguration Registers PCI Address MappingMPC Bus Address Space PCI to MPC Address DecodingRavenMPIC Control Registers Decoder PriorityPCI Slave Command Type Slave Response? Command TypesCommand Types PCI Slave Response AddressingTarget-Initiated Termination Exclusive AccessDevice Selection Fast Back-to-Back TransactionsPCI Write Posting ParityCache Support PCI MasterEntity Addressed PCI Master Command CodesPCI Command Transfer TypeCombining, Merging, and Collapsing Master Initiated TerminationArbitration Arbitration LatencyAddress/Data Stepping Generating PCI Cycles Generating PCI Memory and I/O CyclesPCI Cycle Type Generating PCI Configuration Cycles PCI Spread I/O Address TranslationFunctional Description Generating PCI Special Cycles Device Number Address BitWhen MPC Devices are Big-Endian Endian ConversionGenerating PCI Interrupt Acknowledge Cycles Big- to Little-Endian Data Swap Address Modification for Little-Endian Transfers When MPC Devices are Little-EndianRaven Registers and Endian Mode Data Address Length Bytes ModificationError Handling SMA Error Status Error Address AttributesTransaction Ordering PerrRaven Registers MPC RegistersRaven MPC Register Map Vendor ID/Device ID Registers VenidDevid Revid General Control-Status/Feature RegistersRevision ID Register Revision ID. Identifies the Raven revision level. ThisMarb FlbrdBhog MpicMIDx FeatCurrent MPC Data Bus Master Operation Reset $00 $B4 Prescaler Adjust RegisterOperation Reset $00 MPC Arbiter Control RegisterMPC Error Enable Register MatomMatoi SmamRtam PerriMPC Error Status Register OVFMato PCI transaction. The bit may be cleared by writing it to a Writing it to a 0 has no effect. When the Smam bitSMA RTARegister MPC Error Attribute Register MeratWhich originated the transfer in which the error occurred TTxDesignates a selected byte Piack Operation Reset $0000PCI Interrupt Acknowledge Register Address $FEFF0030 Bit NameEND Operation Reset $8000 $8080Start MPC Slave Address 3 RegisterREN MPC Slave Offset/Attribute 0,1 and 2 RegistersMSOFFx WENWpen IOMMSOFF3 Cycles. When clear, the corresponding MPC slave will PCI Registers$18 $7F Raven PCI Configuration Register Map$0C $8C$CF8 Operation Reset $4801 $1057Raven PCI I/O Register Map Offset $00 Bit NamePCI Command/ Status Registers Sigta DparSeltim RcvtaBase Register Revision ID/ Class Code RegistersClass SpaceIO/MEM RESIoba PRETo access MPC bus resources. The value of this field will PCI Slave Address 0,1,2 and 3 RegistersBe compared with the upper 16 bits of the incoming PCI Transfer type code which specifies the current transaction PCI Slave Attribute/ Offset 0,1,2 and 3 RegistersINV GBLConfigaddress Register Perspective from the MPC bus in Big-Endian modeConceptual perspective from the PCI bus FUN Perspective from the MPC bus in Little-Endian modeREG DEVEN Enable Configdata RegisterBUS Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation Reset Data ‘B’ Data ‘C’ Data ‘D’ Operation ResetFeatures Raven Interrupt ControllerArchitecture Readability of CSR Interrupt Source PriorityProcessor’s Current Task Priority Interprocessor Interrupts IPI Nesting of Interrupt EventsSpurious Vector Generation CompatibilityRaven-Detected Errors TimersInterrupt Delivery Modes Block Diagram Description Raven Interrupt ControllerProgram-Visible Registers Interrupt Pending Register IPRInterrupt Selector is In-Service Register ISR Interrupt Request Register IRRInterrupt Router Raven PCI Bridge Asic 10. RavenMPIC Register Map Mpic RegistersRavenMPIC Registers Off$010E0 $010F0$011E0 $100E0 $100F0$101E0 $101F0Feature Reporting Register NcpuVID Global Configuration Register Offset $01020 Bit NameSTP Processor 1. Writing a 1 to P1 will assert the Soft ResetVendor Identification Register Processor Init RegisterACT IPI Vector/Priority RegistersMask PriorVector fetch Spurious Vector RegisterInterrupt Acknowledge register is read during a spurious Offset $010E0 Bit NameTimer Current Count Registers Timer Base Count RegistersBase Count. This field contains the 31-bit count for this Count Inhibit. Setting this bit to 1 inhibits counting forThis timer. Setting the bit to 0 allows counting to proceed Bit transitions from a 1 to a 0, the value is copied intoTimer Destination Registers POL Setting this bit to a 0 enables active low or negative edgeExternal Source Vector/Priority Registers SenseExternal Source Destination Registers Raven-Detected Errors Vector/Priority Register Offset $10200 Bit NameRaven-Detected Errors Destination Register Offset $10210 Bit NameOffset Processor $20080 $21080 Bit Name End-of-Interrupt Registers Zero is assumed. Writing to this register signals the endInterrupt Acknowledge Registers End Of Interrupt. There is one EOI register perExternal Interrupt Service Programming NotesReset State Dynamically Changing I/O Interrupt Configuration Interprocessor InterruptsMode EOI RegisterInterrupt Acknowledge Register Current Task Priority LevelArchitectural Notes Page Features of the Falcon Chip Set DramBlock Diagrams Falcon Pair Used with Dram in a SystemFalcon Internal Data Paths Simplified Overall Dram Connections Bit Ordering Convention PerformanceFour-beat Reads/Writes Single-beat Reads/Writes Dram Speeds2nd 3rd 4th PowerPC 60x Bus to Dram Access Timing 70ns Page DevicesClock Periods Required For Total Access Type BeatPowerPC 60x Bus to Dram Access Timing 60ns Page Devices 2nd 3rd 4th Clocks BeatPowerPC Bus to Dram Access Timing 50ns Hyper Devices ROM/Flash Speeds Completing Data Transfers PowerPC 60x Bus InterfaceResponding to Address Transfers Cache CoherencyCache Coherency Restrictions L2 Cache SupportCycle Types Error Reporting Single-BitError Logging Dram TesterROM/Flash Interface Functional Description $XXFFFFFA $7FFFFE $XXFFFFF8 $7FFFFC$XXFFFFF9 $7FFFFD $XXFFFFFB $7FFFFF$X3FFFFF2 $7FFFFE $X3FFFFF0 $7FFFFE$X3FFFFF1 $7FFFFE $X3FFFFF3 $7FFFFERefresh/Scrub Blocks a and/or B Present, Blocks C and D Not PresentBlocks a and/or B Present, Blocks C and/or D Present Chip Defaults Dram ArbitrationCSR Accesses External Register SetCSR Architecture Data Path for Reads from the Falcon Internal CSRs Data Path for Writes to the Falcon Internal CSRs Memory Map for Byte Reads to CSR 1906 Memory Map for 4-Byte Reads to CSR Register Summary Detailed Register Bit Descriptions10. Register Summary Programming Model Test D3 Lower 32 BitsVendor/Device Register Address $FEF80000 Bit NameRevision ID/ General Control Register Read Zero Read onlyRam spd0,ram spd1 11. ram spd1,ram spd0 and Dram TypeRam spd0, ram spd1 Dram Speed Dram Type Dram Attributes Register Ram a/b/c/d enRam a/b/c/d siz0-2 0MB BlockA/B/C/D ConfigurationsRam a/b/c/d Block Size Devices Used Technology Comments SIMM/DIMMCLK Frequency Register Dram Base RegisterRAM A/B/C/D Base CLK FrequencyRwcb ECC Control RegisterRefdis Read Zero11707.00 Falcon ECC Memory Controller Chip Set Mien TienSien MckenElog Esen EmbtError Address Register Address $FEF80038 Bit NameRtest0,rtest1,rtest2 Test Mode selected 13. rtest EncodingsRefresh/Scrub Address Register Address $FEF80048 Bit NameROM a Base 1Mbyte of Block a also appears at $FFF00000Rom a siz Block Size 14. ROM Block a Size Encoding15. romarv and rombrv Encoding 1MB16. Read/Write to ROM/Flash Cycle Transfer Alignment Romx64 Romxwe Falcon ResponseROM B Base/Size Register ROM B Base1Mbyte of Block B also appears at $FFF00000 17. ROM Block B Size Encoding Rom b siz Block SizeCTR32 is a 32-bit, free-running counter that increments Dram Tester Control RegistersBit Counter Has been programmed properly. Notice that CTR32 isPower-Up Reset Status Register Address $FEF80400 Bit NameAddress $FEF80500 Bit Name External Register Set Address $FEF88000 $FEF8FFF8 Bit NameProgramming ROM/Flash Devices Parity Checking on the PowerPC BusSoftware Considerations Writing to the Control RegistersSizing Dram Software Considerations 1024MB 256MB 128MB 64MB 32MB 16MB 19. PowerPC 60x Address to Dram Address Mappings18. Sizing Addresses ROW20. Syndrome Codes Ordered by Bit in Error ECC CodesBit Syndrome 20. Syndrome Codes Ordered by Bit in Error 21. Single-Bit Errors Ordered by Syndrome Code $AF $CF $EF10. PowerPC Data to Dram Data Correspondence Data Paths22. PowerPC Data to Dram Data Mapping Page Universe VMEbus to PCI Chip Features of the Universe Asic − BLT, ADOH, RMW, LockBlock Diagram Architectural Diagram for the Universe Universe as VMEbus SlavePCI Bus Interface Universe as VMEbus MasterInterrupter Universe as PCI Slave Universe as PCI MasterDMA Controller VMEbus Interrupt HandlingUniverse Control and Status Registers Ucsr Ucsr Access Mechanisms Universe Register Map Offset Register Name LSI2TO LSI2BSLSI2BD LSI3BSDllue DcppDgcs LintenVSI2CTL F2C VSI0BD F0CVSI1BS F1C VSI2BSUniverse Chip Problems after PCI Reset DescriptionWorkarounds MethodExample 1 MVME2600 Series Board Exhibits PCI Reset Problem ExamplesExample 2 MVME3600 Series Board Acts Differently Run the init code and the LSI0 registers become Example 3 Universe Chip is Checked at Tundra Universe VMEbus to PCI Chip Pci Bus Request PCI Masters PCI ArbitrationPCI Arbitration Assignments PIBInterrupt Handling MVME2300 Series Interrupt ArchitectureEdge Polarity Interrupt Source RavenMPICRavenMPIC Interrupt Assignments LevelInterrupts IRQ14IRQ15 PIB Interrupt Handler Block Diagram PIB PCI/ISA Interrupt Assignments EdgeISA DMA Channels Sources of Reset Reset switchExceptions Sources of Reset Soft ResetReset Sources and Devices Affected Devices AffectedError Notification and Handling Error Notification and HandlingCause Action Endian Issues Big-Endian ModeLittle-Endian Mode PCI Domain Processor/Memory DomainRole of the Raven Asic PCI/EthernetRole of the Universe Asic VMEbus DomainPCI-Graphics ROM/Flash Bank Default Default Mapping for FFF00000-FFFFFFFFROM/Flash Initialization Page Motorola Computer Group Documents Document Title Publication NumberManufacturers’ Documents Document Title and Source Publication NumberMPCFPE/AD EK-DE500-OMRelated Specifications ANSI/IEEEIEC 821 BUS MPR-PPC-RPU-02 IsbnTIA/EIA-232 Page Glossary O S S a R Y Enhanced Integrated Drive Electronics. An improved version PCI. Used in the reference platform specification. IBM Computers developed by the IBM Corporation. PowerPC is IBMSignal Computing System Architecture. a hardware model for See 10base-2 Page Index PCI 1-13 processor IN-3 MPC PCIIN-5 Configaddress 2-56CONFIGDATA IN-7 IN-8