2

Raven PCI Bridge ASIC

FLBRD

Flush Before Read. If set, the Raven will guarantee that

 

all PCI-initiated posted write transactions will complete

 

before any MPC-initiated read transactions are allowed to

 

complete. When FLBRD is clear, there is no correlation

 

between these transaction types and their order of

 

completion. Please refer to the Transaction Ordering

 

section for more information.

BHOG

Bus Hog. If set, the Raven MPC master will operate in the

 

Bus Hog mode. Bus Hog mode means the MPC master

 

will continually request the MPC bus for the entire

 

duration of each PCI transfer. If Bus Hog is not enabled,

 

the MPC master will request the bus in a normal manner.

 

Please refer to the MPC Master section for more

 

information.

 

 

MBTx

MPC Bus Time-out.Specifies the MPC bus time-out

 

length. The time-out length is encoded as follows:

 

 

 

 

 

 

 

MBT

Time-Out Length

 

 

 

 

 

 

 

 

00

256 μsec

 

 

 

 

 

 

 

 

01

64 μsec

 

 

 

 

 

 

 

 

10

8 μsec

 

 

 

 

 

 

 

 

11

Disabled

 

 

 

 

 

 

P64

64-bit PCI Mode Enable. If set, the Raven is connected

 

to a 64-bit PCI bus. This bit is set if REQ64∗ is asserted

 

on the rising edge of RESET∗.

MARB

MPC Arbiter Enable. If set, the Raven internal MPC

 

Arbiter is enabled. This bit is set if CPUID is %111 on the

 

rising edge of RESET∗.

MPIC

Multi-Processor Interrupt Controller Enable. If set,

 

the Raven internal MPIC interrupt controller is enabled.

This bit is set if EXT15 is high on the rising edge of RESET∗. If cleared, Raven-detected errors are passed on to the processor 0 INT pin.

2-34

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Motorola MVME2300 Series manual Flbrd, Bhog, Marb, Mpic