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Motorola MVME2300 Series manual Architectural Notes, Raven Interrupt Controller

Models: MVME2300 Series

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	Raven Interrupt Controller
Architectural Notes	2
	2

The hardware and software overhead required to update the Task Priority register synchronously with instruction execution may far outweigh the anticipated benefits of the Task Priority register. To minimize this overhead, the interrupt controller architecture should allow the Task Priority register to be updated asynchronously with respect to instruction execution. Lower-priority interrupts may continue to occur for an indeterminate number of cycles after the processor has updated the Task Priority register. If this is not acceptable, the interrupt controller architecture should recommend that if the Task Priority register is not implemented with the processor, the Task Priority register should be updated only when the processor enter or exits an idle state.

Only when the Task Priority register is integrated within the processor, (such that it can be accessed as quickly as the MSRee bit defined in the Programming Notes section, for example), should the architecture require the Task Priority register to be updated synchronously with instruction execution.

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Motorola MVME2300 Series manual Architectural Notes, Raven Interrupt Controller

Contents

MVME2300 Series VME Processor Module Programmer’s Reference GuidePage Safety Summary Instructions FlammabilityCE Notice European Community Limited and Restricted Rights Legend Contents Raven PCI Bridge Asic Page Page Falcon ECC Memory Controller Chip Set Universe VMEbus to PCI Chip Chapter Page List of Figures Page List of Tables Xviii 16MB ECC Dram Model Memory Processor32MB ECC Dram 64MB ECC DramDate Description of Change Summary of ChangesComments and Suggestions Overview of ContentsBold Conventions Used in This ManualEnter, Return or CR CtrlXxiii Xxiv Overview IntroductionFeatures MVME2300 Series Summary of FeaturesFeature MVME2300 ECC DramScsa I/O System Block DiagramBoard Description and Memory Maps MVME2300 Series System Block Diagram Front Panel Functional DescriptionVMEbus Interface PCI interface Programming ModelProcessor Memory Maps P2 I/OProcessor Address Size Definition Start End Default Processor Memory MapChrp Memory Map Example Processor Chrp Memory MapAddress Register Name Register Value Raven MPC Register Values for Chrp Memory MapBfff Ffff Processor Prep Memory MapPrep Memory Map Example Raven MPC Register Values for Prep Memory Map PCI Configuration AccessPCI Memory Maps Default PCI Memory MapPCI Chrp Memory Map PCI Address Size Definition Start EndFC03 Ffff Universe PCI Register Values for Chrp Memory Map Configuration Register Value Address Offset Register NameRaven PCI Register Values for Chrp Memory Map 10. PCI Prep Memory Map PCI Prep Memory Map39FE Ffff 38FF Ffff39FF Ffff 3AFE Ffff11. Raven PCI Register Values for Prep Memory Map 12. Universe PCI Register Values for Prep Memory Map VMEbus Master Map VMEbus MappingVMEbus Slave Map VMEbus Slave Mapping VSI0BS VSI0CTLVSI0BD VSI0TOFalcon-Controlled System Registers VMEbus Address Size Chrp Map Prep Map Range Mode14. VMEbus Slave Map Example 15. System Register SummarySystem Configuration Register $FEF80400 System Configuration Register Syscr$FD Sysclk Value System Clock Speed PCI Clock SpeedP0/1STAT Value Processor 0/1 Present External In-line Cache Memory Configuration Register $FEF80404 Memory Configuration Register MemcrMSIZE01 MSIZE01 Total Memory On BoardL2TYPE03 MSPD01RA/BTYP02 FLSHP02 L2PLL03System External Cache Control Register Sxccr PLL Value SizeProcessor 1 External Cache Control Register P1XCCR Processor 0 External Cache Control Register P0XCCRCPU Control Register CPU Control Register $FEF88300ISA Local Resource Bus Access RegistersW83C553 PIB Registers UartGeneral-Purpose Readable Jumpers NVRAM/RTC and Watchdog Timer Registers17. M48T59/559 Access Registers Module Configuration and Status Registers18. Module Configuration and Status Registers PCI I/O Address FunctionOld CPU Configuration Register $FE000800 CPU Configuration RegisterCputype SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0Pcixp PMC2P PMC1P Vmep Lanp Base Module Feature RegisterBase Module Feature Register Offset $0802 Basetype Base Module Status Register BmsrBase Module Status Register Offset $0803 BasetypeSeven-Segment Display Register VME RegistersSegment Display Register Offset $08C0 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0LM/SIG Control Register 19. VME RegistersSETSIG1 SETSIG0LM/SIG Status Register Board Description and Memory Maps Location Monitor Lower Base Address Register Location Monitor Upper Base Address RegisterLocation Monitor Upper Base Address Register Offset $1002 Location Monitor Lower Base Address Register Offset $1003Semaphore Register 1 Offset $1004 Semaphore RegisterSEM1 Semaphore Register 2 Offset $100520. Emulated Z8536 Access Registers Emulated Z8536 CIO Registers and Port PinsVME Geographical Address Register Vgar Emulated Z8536 Registers21. Z8536 CIO Port Pin Assignments Z8536 CIO Port PinsPort Signal Direction Descriptions Pin Name PC3 BASETYP1 ISA DMA ChannelsPC2 BASETYP0 Page Function Features FeaturesFeatures of the Raven Asic Block Diagram Raven Block Diagram MPC Address Mapping MPC Bus InterfaceMPC-to-PCI Address Decoding MPC Slave MPC to PCI Address TranslationMPC Transfer Type Transaction Encoding Command Types MPC Slave ResponseMPC Master MPC Write PostingMPC Transfer Type MPC Transfer Size TT0-TT4 PCI Command CodeMPC Transfer Types MPC Arbiter MPC Bus TimerPCI Address Mapping Configuration RegistersPCI to MPC Address Decoding MPC Bus Address SpaceDecoder Priority RavenMPIC Control RegistersPCI Slave Command Types PCI Slave Response Command TypesCommand Type Slave Response? AddressingDevice Selection Exclusive AccessTarget-Initiated Termination Fast Back-to-Back TransactionsCache Support ParityPCI Write Posting PCI MasterPCI Command PCI Master Command CodesEntity Addressed Transfer TypeMaster Initiated Termination Combining, Merging, and CollapsingAddress/Data Stepping ArbitrationArbitration Latency PCI Cycle Type Generating PCI CyclesGenerating PCI Memory and I/O Cycles PCI Spread I/O Address Translation Generating PCI Configuration CyclesFunctional Description Device Number Address Bit Generating PCI Special CyclesGenerating PCI Interrupt Acknowledge Cycles When MPC Devices are Big-EndianEndian Conversion Big- to Little-Endian Data Swap Raven Registers and Endian Mode When MPC Devices are Little-EndianAddress Modification for Little-Endian Transfers Data Address Length Bytes ModificationError Handling Transaction Ordering Error Status Error Address AttributesSMA PerrMPC Registers Raven RegistersRaven MPC Register Map Devid Vendor ID/Device ID RegistersVenid Revision ID Register General Control-Status/Feature RegistersRevid Revision ID. Identifies the Raven revision level. ThisBhog FlbrdMarb MpicCurrent MPC Data Bus Master MIDxFeat Operation Reset $00 Prescaler Adjust RegisterOperation Reset $00 $B4 MPC Arbiter Control RegisterMatom MPC Error Enable RegisterRtam SmamMatoi PerriMato MPC Error Status RegisterOVF SMA Writing it to a 0 has no effect. When the Smam bitPCI transaction. The bit may be cleared by writing it to a RTAWhich originated the transfer in which the error occurred MPC Error Attribute Register MeratRegister TTxDesignates a selected byte PCI Interrupt Acknowledge Register Operation Reset $0000Piack Address $FEFF0030 Bit NameStart Operation Reset $8000 $8080END MPC Slave Address 3 RegisterMSOFFx MPC Slave Offset/Attribute 0,1 and 2 RegistersREN WENMSOFF3 WpenIOM PCI Registers Cycles. When clear, the corresponding MPC slave will$0C Raven PCI Configuration Register Map$18 $7F $8CRaven PCI I/O Register Map Operation Reset $4801 $1057$CF8 Offset $00 Bit NamePCI Command/ Status Registers Seltim DparSigta RcvtaClass Revision ID/ Class Code RegistersBase Register SpaceIoba RESIO/MEM PREBe compared with the upper 16 bits of the incoming PCI To access MPC bus resources. The value of this field willPCI Slave Address 0,1,2 and 3 Registers INV PCI Slave Attribute/ Offset 0,1,2 and 3 RegistersTransfer type code which specifies the current transaction GBLConceptual perspective from the PCI bus Configaddress RegisterPerspective from the MPC bus in Big-Endian mode REG Perspective from the MPC bus in Little-Endian modeFUN DEVBUS EN EnableConfigdata Register Data ‘B’ Data ‘C’ Data ‘D’ Operation Reset Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation ResetArchitecture FeaturesRaven Interrupt Controller Processor’s Current Task Priority Readability of CSRInterrupt Source Priority Spurious Vector Generation Nesting of Interrupt EventsInterprocessor Interrupts IPI CompatibilityTimers Raven-Detected ErrorsInterrupt Delivery Modes Raven Interrupt Controller Block Diagram DescriptionInterrupt Selector is Program-Visible RegistersInterrupt Pending Register IPR Interrupt Router In-Service Register ISRInterrupt Request Register IRR Raven PCI Bridge Asic RavenMPIC Registers Mpic Registers10. RavenMPIC Register Map Off$011E0 $010E0$010F0 $100F0 $100E0$101F0 $101E0VID Feature Reporting RegisterNcpu Offset $01020 Bit Name Global Configuration RegisterVendor Identification Register Processor 1. Writing a 1 to P1 will assert the Soft ResetSTP Processor Init RegisterMask IPI Vector/Priority RegistersACT PriorInterrupt Acknowledge register is read during a spurious Spurious Vector RegisterVector fetch Offset $010E0 Bit NameTimer Base Count Registers Timer Current Count RegistersThis timer. Setting the bit to 0 allows counting to proceed Count Inhibit. Setting this bit to 1 inhibits counting forBase Count. This field contains the 31-bit count for this Bit transitions from a 1 to a 0, the value is copied intoTimer Destination Registers External Source Vector/Priority Registers Setting this bit to a 0 enables active low or negative edgePOL SenseExternal Source Destination Registers Offset $10200 Bit Name Raven-Detected Errors Vector/Priority RegisterOffset $10210 Bit Name Raven-Detected Errors Destination RegisterOffset Processor $20080 $21080 Bit Name Interrupt Acknowledge Registers Zero is assumed. Writing to this register signals the endEnd-of-Interrupt Registers End Of Interrupt. There is one EOI register perProgramming Notes External Interrupt ServiceReset State Interprocessor Interrupts Dynamically Changing I/O Interrupt ConfigurationInterrupt Acknowledge Register EOI RegisterMode Current Task Priority LevelArchitectural Notes Page Dram Features of the Falcon Chip SetFalcon Pair Used with Dram in a System Block DiagramsFalcon Internal Data Paths Simplified Overall Dram Connections Four-beat Reads/Writes Bit Ordering ConventionPerformance Dram Speeds Single-beat Reads/WritesClock Periods Required For Total Access Type PowerPC 60x Bus to Dram Access Timing 70ns Page Devices2nd 3rd 4th Beat2nd 3rd 4th Clocks Beat PowerPC 60x Bus to Dram Access Timing 60ns Page DevicesPowerPC Bus to Dram Access Timing 50ns Hyper Devices ROM/Flash Speeds Responding to Address Transfers PowerPC 60x Bus InterfaceCompleting Data Transfers Cache CoherencyCycle Types Cache Coherency RestrictionsL2 Cache Support Single-Bit Error ReportingROM/Flash Interface Error LoggingDram Tester Functional Description $XXFFFFF9 $7FFFFD $XXFFFFF8 $7FFFFC$XXFFFFFA $7FFFFE $XXFFFFFB $7FFFFF$X3FFFFF1 $7FFFFE $X3FFFFF0 $7FFFFE$X3FFFFF2 $7FFFFE $X3FFFFF3 $7FFFFEBlocks a and/or B Present, Blocks C and D Not Present Refresh/ScrubBlocks a and/or B Present, Blocks C and/or D Present Dram Arbitration Chip DefaultsCSR Architecture CSR AccessesExternal Register Set Data Path for Reads from the Falcon Internal CSRs Data Path for Writes to the Falcon Internal CSRs Memory Map for Byte Reads to CSR 1906 Memory Map for 4-Byte Reads to CSR Detailed Register Bit Descriptions Register Summary10. Register Summary Test D3 Lower 32 Bits Programming ModelAddress $FEF80000 Bit Name Vendor/Device RegisterRead Zero Read only Revision ID/ General Control RegisterRam spd0, ram spd1 Dram Speed Dram Type Ram spd0,ram spd111. ram spd1,ram spd0 and Dram Type Ram a/b/c/d siz0-2 Dram Attributes RegisterRam a/b/c/d en Ram a/b/c/d Block Size Devices Used Technology Comments BlockA/B/C/D Configurations0MB SIMM/DIMMRAM A/B/C/D Base Dram Base RegisterCLK Frequency Register CLK FrequencyRefdis ECC Control RegisterRwcb Read Zero11707.00 Falcon ECC Memory Controller Chip Set Sien TienMien MckenElog Embt EsenAddress $FEF80038 Bit Name Error Address Register13. rtest Encodings Rtest0,rtest1,rtest2 Test Mode selectedAddress $FEF80048 Bit Name Refresh/Scrub Address Register1Mbyte of Block a also appears at $FFF00000 ROM a Base15. romarv and rombrv Encoding 14. ROM Block a Size EncodingRom a siz Block Size 1MBCycle Transfer Alignment Romx64 Romxwe Falcon Response 16. Read/Write to ROM/Flash1Mbyte of Block B also appears at $FFF00000 ROM B Base/Size RegisterROM B Base Rom b siz Block Size 17. ROM Block B Size EncodingBit Counter Dram Tester Control RegistersCTR32 is a 32-bit, free-running counter that increments Has been programmed properly. Notice that CTR32 isAddress $FEF80500 Bit Name Power-Up Reset Status RegisterAddress $FEF80400 Bit Name Address $FEF88000 $FEF8FFF8 Bit Name External Register SetSoftware Considerations Parity Checking on the PowerPC BusProgramming ROM/Flash Devices Writing to the Control RegistersSizing Dram Software Considerations 18. Sizing Addresses 19. PowerPC 60x Address to Dram Address Mappings1024MB 256MB 128MB 64MB 32MB 16MB ROWBit Syndrome 20. Syndrome Codes Ordered by Bit in ErrorECC Codes 20. Syndrome Codes Ordered by Bit in Error $AF $CF $EF 21. Single-Bit Errors Ordered by Syndrome CodeData Paths 10. PowerPC Data to Dram Data Correspondence22. PowerPC Data to Dram Data Mapping Page Universe VMEbus to PCI Chip − BLT, ADOH, RMW, Lock Features of the Universe AsicBlock Diagram Universe as VMEbus Slave Architectural Diagram for the UniverseUniverse as VMEbus Master PCI Bus InterfaceUniverse as PCI Slave Universe as PCI Master InterrupterVMEbus Interrupt Handling DMA ControllerUniverse Control and Status Registers Ucsr Ucsr Access Mechanisms Universe Register Map Offset Register Name LSI2BD LSI2BSLSI2TO LSI3BSDgcs DcppDllue LintenVSI1BS F1C VSI0BD F0CVSI2CTL F2C VSI2BSDescription Universe Chip Problems after PCI ResetMethod WorkaroundsExamples Example 1 MVME2600 Series Board Exhibits PCI Reset ProblemExample 2 MVME3600 Series Board Acts Differently Run the init code and the LSI0 registers become Example 3 Universe Chip is Checked at Tundra Universe VMEbus to PCI Chip PCI Arbitration Assignments PCI ArbitrationPci Bus Request PCI Masters PIBMVME2300 Series Interrupt Architecture Interrupt HandlingRavenMPIC Interrupt Assignments RavenMPICEdge Polarity Interrupt Source LevelIRQ15 InterruptsIRQ14 PIB Interrupt Handler Block Diagram Edge PIB PCI/ISA Interrupt AssignmentsISA DMA Channels Exceptions Sources of ResetReset switch Reset Sources and Devices Affected Soft ResetSources of Reset Devices AffectedCause Action Error Notification and HandlingError Notification and Handling Big-Endian Mode Endian IssuesLittle-Endian Mode Role of the Raven Asic Processor/Memory DomainPCI Domain PCI/EthernetPCI-Graphics Role of the Universe AsicVMEbus Domain ROM/Flash Initialization ROM/Flash Bank DefaultDefault Mapping for FFF00000-FFFFFFFF Page Document Title Publication Number Motorola Computer Group DocumentsDocument Title and Source Publication Number Manufacturers’ DocumentsEK-DE500-OM MPCFPE/ADIEC 821 BUS Related SpecificationsANSI/IEEE TIA/EIA-232 MPR-PPC-RPU-02Isbn Page Glossary O S S a R Y Enhanced Integrated Drive Electronics. An improved version PCI. Used in the reference platform specification. IBM IBM Computers developed by the IBM Corporation. PowerPC isSignal Computing System Architecture. a hardware model for See 10base-2 Page Index PCI 1-13 processor IN-3 PCI MPCIN-5 Configaddress 2-56CONFIGDATA IN-7 IN-8