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Motorola MVME2300 Series manual MIDx, Feat, Current MPC Data Bus Master

Models: MVME2300 Series

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Page 105

			Raven Registers

MIDx	Master ID. Encoded as shown below to indicate who is
	currently the MPC bus master. When the internal MPC
	arbiter is enabled (MARB is set), these bits are controlled
	by the internal arbiter. When the internal arbiter is
	disabled (MARB is clear) these bits reflect the status of
	the CPUID pins. In a multi- processor environment, these
	bits allow software to determine on which processor it is
	currently running. The internal MPC arbiter encodes this
	field as follows:
.
		MID	Current MPC Data Bus Master

		00	Device on ABG0*

		01	Device on ABG1*

		10	Device on ABG2

		11	Raven

FEAT	Feature Register. Each bit in this register reflects the

state of one of the external interrupt input pins on the rising edge of RESET∗. This register may be used to report hardware configuration parameters to system software.

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Motorola MVME2300 Series manual MIDx, Feat, Current MPC Data Bus Master

Contents

MVME2300 Series VME Processor Module Programmer’s Reference GuidePage Safety Summary Instructions FlammabilityCE Notice European Community Limited and Restricted Rights Legend Contents Raven PCI Bridge Asic Page Page Falcon ECC Memory Controller Chip Set Universe VMEbus to PCI Chip Chapter Page List of Figures Page List of Tables Xviii 16MB ECC Dram Model Memory Processor32MB ECC Dram 64MB ECC DramDate Description of Change Summary of ChangesComments and Suggestions Overview of ContentsBold Conventions Used in This ManualEnter, Return or CR CtrlXxiii Xxiv Overview IntroductionFeatures MVME2300 Series Summary of FeaturesFeature MVME2300 ECC DramScsa I/O System Block DiagramBoard Description and Memory Maps MVME2300 Series System Block Diagram Functional Description VMEbus InterfaceFront Panel PCI interface Programming ModelProcessor Memory Maps P2 I/OProcessor Address Size Definition Start End Default Processor Memory MapChrp Memory Map Example Processor Chrp Memory MapAddress Register Name Register Value Raven MPC Register Values for Chrp Memory MapProcessor Prep Memory Map Prep Memory Map ExampleBfff Ffff Raven MPC Register Values for Prep Memory Map PCI Configuration AccessPCI Memory Maps Default PCI Memory MapPCI Chrp Memory Map PCI Address Size Definition Start EndFC03 Ffff Configuration Register Value Address Offset Register Name Raven PCI Register Values for Chrp Memory MapUniverse PCI Register Values for Chrp Memory Map 10. PCI Prep Memory Map PCI Prep Memory Map39FE Ffff 38FF Ffff39FF Ffff 3AFE Ffff11. Raven PCI Register Values for Prep Memory Map 12. Universe PCI Register Values for Prep Memory Map VMEbus Master Map VMEbus MappingVMEbus Slave Map VMEbus Slave Mapping VSI0BS VSI0CTLVSI0BD VSI0TOFalcon-Controlled System Registers VMEbus Address Size Chrp Map Prep Map Range Mode14. VMEbus Slave Map Example 15. System Register SummarySystem Configuration Register $FEF80400 System Configuration Register Syscr$FD Sysclk Value System Clock Speed PCI Clock SpeedP0/1STAT Value Processor 0/1 Present External In-line Cache Memory Configuration Register $FEF80404 Memory Configuration Register MemcrMSIZE01 MSIZE01 Total Memory On BoardMSPD01 RA/BTYP02L2TYPE03 FLSHP02 L2PLL03System External Cache Control Register Sxccr PLL Value SizeProcessor 1 External Cache Control Register P1XCCR Processor 0 External Cache Control Register P0XCCRCPU Control Register CPU Control Register $FEF88300ISA Local Resource Bus Access RegistersW83C553 PIB Registers UartGeneral-Purpose Readable Jumpers NVRAM/RTC and Watchdog Timer Registers17. M48T59/559 Access Registers Module Configuration and Status Registers18. Module Configuration and Status Registers PCI I/O Address FunctionOld CPU Configuration Register $FE000800 CPU Configuration RegisterCputype SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0Base Module Feature Register Base Module Feature Register Offset $0802Pcixp PMC2P PMC1P Vmep Lanp Basetype Base Module Status Register BmsrBase Module Status Register Offset $0803 BasetypeSeven-Segment Display Register VME RegistersSegment Display Register Offset $08C0 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0LM/SIG Control Register 19. VME RegistersSETSIG1 SETSIG0LM/SIG Status Register Board Description and Memory Maps Location Monitor Lower Base Address Register Location Monitor Upper Base Address RegisterLocation Monitor Upper Base Address Register Offset $1002 Location Monitor Lower Base Address Register Offset $1003Semaphore Register 1 Offset $1004 Semaphore RegisterSEM1 Semaphore Register 2 Offset $100520. Emulated Z8536 Access Registers Emulated Z8536 CIO Registers and Port PinsVME Geographical Address Register Vgar Emulated Z8536 RegistersZ8536 CIO Port Pins Port Signal Direction Descriptions Pin Name21. Z8536 CIO Port Pin Assignments ISA DMA Channels PC2 BASETYP0PC3 BASETYP1 Page Features Features of the Raven AsicFunction Features Block Diagram Raven Block Diagram MPC Address Mapping MPC Bus InterfaceMPC-to-PCI Address Decoding MPC Slave MPC to PCI Address TranslationMPC Transfer Type Transaction Encoding Command Types MPC Slave ResponseMPC Master MPC Write PostingPCI Command Code MPC Transfer TypesMPC Transfer Type MPC Transfer Size TT0-TT4 MPC Arbiter MPC Bus TimerPCI Address Mapping Configuration RegistersPCI to MPC Address Decoding MPC Bus Address SpaceDecoder Priority RavenMPIC Control RegistersPCI Slave Command Types PCI Slave Response Command TypesCommand Type Slave Response? AddressingDevice Selection Exclusive AccessTarget-Initiated Termination Fast Back-to-Back TransactionsCache Support ParityPCI Write Posting PCI MasterPCI Command PCI Master Command CodesEntity Addressed Transfer TypeMaster Initiated Termination Combining, Merging, and CollapsingArbitration Arbitration LatencyAddress/Data Stepping Generating PCI Cycles Generating PCI Memory and I/O CyclesPCI Cycle Type PCI Spread I/O Address Translation Generating PCI Configuration CyclesFunctional Description Device Number Address Bit Generating PCI Special CyclesWhen MPC Devices are Big-Endian Endian ConversionGenerating PCI Interrupt Acknowledge Cycles Big- to Little-Endian Data Swap Raven Registers and Endian Mode When MPC Devices are Little-EndianAddress Modification for Little-Endian Transfers Data Address Length Bytes ModificationError Handling Transaction Ordering Error Status Error Address AttributesSMA PerrMPC Registers Raven RegistersRaven MPC Register Map Vendor ID/Device ID Registers VenidDevid Revision ID Register General Control-Status/Feature RegistersRevid Revision ID. Identifies the Raven revision level. ThisBhog FlbrdMarb MpicMIDx FeatCurrent MPC Data Bus Master Operation Reset $00 Prescaler Adjust RegisterOperation Reset $00 $B4 MPC Arbiter Control RegisterMatom MPC Error Enable RegisterRtam SmamMatoi PerriMPC Error Status Register OVFMato SMA Writing it to a 0 has no effect. When the Smam bitPCI transaction. The bit may be cleared by writing it to a RTAWhich originated the transfer in which the error occurred MPC Error Attribute Register MeratRegister TTxDesignates a selected byte PCI Interrupt Acknowledge Register Operation Reset $0000Piack Address $FEFF0030 Bit NameStart Operation Reset $8000 $8080END MPC Slave Address 3 RegisterMSOFFx MPC Slave Offset/Attribute 0,1 and 2 RegistersREN WENWpen IOMMSOFF3 PCI Registers Cycles. When clear, the corresponding MPC slave will$0C Raven PCI Configuration Register Map$18 $7F $8CRaven PCI I/O Register Map Operation Reset $4801 $1057$CF8 Offset $00 Bit NamePCI Command/ Status Registers Seltim DparSigta RcvtaClass Revision ID/ Class Code RegistersBase Register SpaceIoba RESIO/MEM PRETo access MPC bus resources. The value of this field will PCI Slave Address 0,1,2 and 3 RegistersBe compared with the upper 16 bits of the incoming PCI INV PCI Slave Attribute/ Offset 0,1,2 and 3 RegistersTransfer type code which specifies the current transaction GBLConfigaddress Register Perspective from the MPC bus in Big-Endian modeConceptual perspective from the PCI bus REG Perspective from the MPC bus in Little-Endian modeFUN DEVEN Enable Configdata RegisterBUS Data ‘B’ Data ‘C’ Data ‘D’ Operation Reset Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation ResetFeatures Raven Interrupt ControllerArchitecture Readability of CSR Interrupt Source PriorityProcessor’s Current Task Priority Spurious Vector Generation Nesting of Interrupt EventsInterprocessor Interrupts IPI CompatibilityTimers Raven-Detected ErrorsInterrupt Delivery Modes Raven Interrupt Controller Block Diagram DescriptionProgram-Visible Registers Interrupt Pending Register IPRInterrupt Selector is In-Service Register ISR Interrupt Request Register IRRInterrupt Router Raven PCI Bridge Asic RavenMPIC Registers Mpic Registers10. RavenMPIC Register Map Off$010E0 $010F0$011E0 $100F0 $100E0$101F0 $101E0Feature Reporting Register NcpuVID Offset $01020 Bit Name Global Configuration RegisterVendor Identification Register Processor 1. Writing a 1 to P1 will assert the Soft ResetSTP Processor Init RegisterMask IPI Vector/Priority RegistersACT PriorInterrupt Acknowledge register is read during a spurious Spurious Vector RegisterVector fetch Offset $010E0 Bit NameTimer Base Count Registers Timer Current Count RegistersThis timer. Setting the bit to 0 allows counting to proceed Count Inhibit. Setting this bit to 1 inhibits counting forBase Count. This field contains the 31-bit count for this Bit transitions from a 1 to a 0, the value is copied intoTimer Destination Registers External Source Vector/Priority Registers Setting this bit to a 0 enables active low or negative edgePOL SenseExternal Source Destination Registers Offset $10200 Bit Name Raven-Detected Errors Vector/Priority RegisterOffset $10210 Bit Name Raven-Detected Errors Destination RegisterOffset Processor $20080 $21080 Bit Name Interrupt Acknowledge Registers Zero is assumed. Writing to this register signals the endEnd-of-Interrupt Registers End Of Interrupt. There is one EOI register perProgramming Notes External Interrupt ServiceReset State Interprocessor Interrupts Dynamically Changing I/O Interrupt ConfigurationInterrupt Acknowledge Register EOI RegisterMode Current Task Priority LevelArchitectural Notes Page Dram Features of the Falcon Chip SetFalcon Pair Used with Dram in a System Block DiagramsFalcon Internal Data Paths Simplified Overall Dram Connections Bit Ordering Convention PerformanceFour-beat Reads/Writes Dram Speeds Single-beat Reads/WritesClock Periods Required For Total Access Type PowerPC 60x Bus to Dram Access Timing 70ns Page Devices2nd 3rd 4th Beat2nd 3rd 4th Clocks Beat PowerPC 60x Bus to Dram Access Timing 60ns Page DevicesPowerPC Bus to Dram Access Timing 50ns Hyper Devices ROM/Flash Speeds Responding to Address Transfers PowerPC 60x Bus InterfaceCompleting Data Transfers Cache CoherencyCache Coherency Restrictions L2 Cache SupportCycle Types Single-Bit Error ReportingError Logging Dram TesterROM/Flash Interface Functional Description $XXFFFFF9 $7FFFFD $XXFFFFF8 $7FFFFC$XXFFFFFA $7FFFFE $XXFFFFFB $7FFFFF$X3FFFFF1 $7FFFFE $X3FFFFF0 $7FFFFE$X3FFFFF2 $7FFFFE $X3FFFFF3 $7FFFFEBlocks a and/or B Present, Blocks C and D Not Present Refresh/ScrubBlocks a and/or B Present, Blocks C and/or D Present Dram Arbitration Chip DefaultsCSR Accesses External Register SetCSR Architecture Data Path for Reads from the Falcon Internal CSRs Data Path for Writes to the Falcon Internal CSRs Memory Map for Byte Reads to CSR 1906 Memory Map for 4-Byte Reads to CSR Detailed Register Bit Descriptions Register Summary10. Register Summary Test D3 Lower 32 Bits Programming ModelAddress $FEF80000 Bit Name Vendor/Device RegisterRead Zero Read only Revision ID/ General Control RegisterRam spd0,ram spd1 11. ram spd1,ram spd0 and Dram TypeRam spd0, ram spd1 Dram Speed Dram Type Dram Attributes Register Ram a/b/c/d enRam a/b/c/d siz0-2 Ram a/b/c/d Block Size Devices Used Technology Comments BlockA/B/C/D Configurations0MB SIMM/DIMMRAM A/B/C/D Base Dram Base RegisterCLK Frequency Register CLK FrequencyRefdis ECC Control RegisterRwcb Read Zero11707.00 Falcon ECC Memory Controller Chip Set Sien TienMien MckenElog Embt EsenAddress $FEF80038 Bit Name Error Address Register13. rtest Encodings Rtest0,rtest1,rtest2 Test Mode selectedAddress $FEF80048 Bit Name Refresh/Scrub Address Register1Mbyte of Block a also appears at $FFF00000 ROM a Base15. romarv and rombrv Encoding 14. ROM Block a Size EncodingRom a siz Block Size 1MBCycle Transfer Alignment Romx64 Romxwe Falcon Response 16. Read/Write to ROM/FlashROM B Base/Size Register ROM B Base1Mbyte of Block B also appears at $FFF00000 Rom b siz Block Size 17. ROM Block B Size EncodingBit Counter Dram Tester Control RegistersCTR32 is a 32-bit, free-running counter that increments Has been programmed properly. Notice that CTR32 isPower-Up Reset Status Register Address $FEF80400 Bit NameAddress $FEF80500 Bit Name Address $FEF88000 $FEF8FFF8 Bit Name External Register SetSoftware Considerations Parity Checking on the PowerPC BusProgramming ROM/Flash Devices Writing to the Control RegistersSizing Dram Software Considerations 18. Sizing Addresses 19. PowerPC 60x Address to Dram Address Mappings1024MB 256MB 128MB 64MB 32MB 16MB ROW20. Syndrome Codes Ordered by Bit in Error ECC CodesBit Syndrome 20. Syndrome Codes Ordered by Bit in Error $AF $CF $EF 21. Single-Bit Errors Ordered by Syndrome CodeData Paths 10. PowerPC Data to Dram Data Correspondence22. PowerPC Data to Dram Data Mapping Page Universe VMEbus to PCI Chip − BLT, ADOH, RMW, Lock Features of the Universe AsicBlock Diagram Universe as VMEbus Slave Architectural Diagram for the UniverseUniverse as VMEbus Master PCI Bus InterfaceUniverse as PCI Slave Universe as PCI Master InterrupterVMEbus Interrupt Handling DMA ControllerUniverse Control and Status Registers Ucsr Ucsr Access Mechanisms Universe Register Map Offset Register Name LSI2BD LSI2BSLSI2TO LSI3BSDgcs DcppDllue LintenVSI1BS F1C VSI0BD F0CVSI2CTL F2C VSI2BSDescription Universe Chip Problems after PCI ResetMethod WorkaroundsExamples Example 1 MVME2600 Series Board Exhibits PCI Reset ProblemExample 2 MVME3600 Series Board Acts Differently Run the init code and the LSI0 registers become Example 3 Universe Chip is Checked at Tundra Universe VMEbus to PCI Chip PCI Arbitration Assignments PCI ArbitrationPci Bus Request PCI Masters PIBMVME2300 Series Interrupt Architecture Interrupt HandlingRavenMPIC Interrupt Assignments RavenMPICEdge Polarity Interrupt Source LevelInterrupts IRQ14IRQ15 PIB Interrupt Handler Block Diagram Edge PIB PCI/ISA Interrupt AssignmentsISA DMA Channels Sources of Reset Reset switchExceptions Reset Sources and Devices Affected Soft ResetSources of Reset Devices AffectedError Notification and Handling Error Notification and HandlingCause Action Big-Endian Mode Endian IssuesLittle-Endian Mode Role of the Raven Asic Processor/Memory DomainPCI Domain PCI/EthernetRole of the Universe Asic VMEbus DomainPCI-Graphics ROM/Flash Bank Default Default Mapping for FFF00000-FFFFFFFFROM/Flash Initialization Page Document Title Publication Number Motorola Computer Group DocumentsDocument Title and Source Publication Number Manufacturers’ DocumentsEK-DE500-OM MPCFPE/ADRelated Specifications ANSI/IEEEIEC 821 BUS MPR-PPC-RPU-02 IsbnTIA/EIA-232 Page Glossary O S S a R Y Enhanced Integrated Drive Electronics. An improved version PCI. Used in the reference platform specification. IBM IBM Computers developed by the IBM Corporation. PowerPC isSignal Computing System Architecture. a hardware model for See 10base-2 Page Index PCI 1-13 processor IN-3 PCI MPCIN-5 Configaddress 2-56CONFIGDATA IN-7 IN-8

MIDx

Current MPC Data Bus Master

FEAT