Motorola MVME2300 Series manual Xviii

Table 3-4. PowerPC Bus to DRAM Access Timing — 50ns Hyper Devices	3-9
Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing — 64 Bits
(32 Bits per Falcon)	3-10
Table 3-6. PowerPC 60x Bus to ROM/Flash Access Timing — 16 Bits (8 Bits
per Falcon)	3-10
Table 3-7. Error Reporting	3-13
Table 3-8. PowerPC 60x to ROM/Flash Address Mapping — ROM/Flash
16 Bits Wide (8 Bits per Falcon)	3-16
Table 3-9. PowerPC 60x to ROM/Flash Address Mapping — ROM/Flash
64 Bits Wide (32 Bits per Falcon)	3-17
Table 3-10. Register Summary	3-28
Table 3-11. ram spd1,ram spd0 and DRAM Type	3-32
Table 3-12. Block_A/B/C/D Configurations	3-34
Table 3-13. rtest Encodings	3-43
Table 3-14. ROM Block A Size Encoding	3-46
Table 3-15. rom_a_rv and rom_b_rv Encoding	3-46
Table 3-16. Read/Write to ROM/Flash	3-47
Table 3-17. ROM Block B Size Encoding	3-49
Table 3-18. Sizing Addresses	3-56
Table 3-19. PowerPC 60x Address to DRAM Address Mappings	3-56
Table 3-20. Syndrome Codes Ordered by Bit in Error	3-57
Table 3-21. Single-Bit Errors Ordered by Syndrome Code	3-59
Table 3-22. PowerPC Data to DRAM Data Mapping	3-61
Table 4-1. Features of the Universe ASIC	4-2
Table 4-2. Universe Register Map	4-10
Table 5-1. PCI Arbitration Assignments	5-1
Table 5-2. RavenMPIC Interrupt Assignments	5-3
Table 5-3. PIB PCI/ISA Interrupt Assignments	5-6
Table 5-4. Reset Sources and Devices Affected	5-9
Table 5-5. Error Notification and Handling	5-10
Table 5-6. ROM/Flash Bank Default	5-15

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