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Motorola MVME2300 Series manual Summary of Changes, Date Description of Change

Models: MVME2300 Series

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This manual is intended for anyone who designs OEM systems, adds capability to an existing compatible system, or works in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. To use this manual, you may also wish to become familiar with the publications listed in Appendix A, Related Documentation.

Summary of Changes

	This is the fifth edition of the Programmer’s Reference Guide. It
	supersedes the March 2001 edition and incorporates the following updates.

Date	Description of Change

January 2001	A caution about DRAM component requirements was added to the DRAM
	Attributes Register and Sizing DRAM sections of Chapter 3.

January 2001	In descriptions of the general-purpose software-readable header (J10/J17), such
	as Figure 1-4in Chapter 1, information on bit 1 (SRH1) was updated to
	correctly reflect the functionality of that bit.

March 2001	At various locations in the manual, such as P2 I/O on page 1-7, information has
	been added to accommodate the MVME2300SC variants of the board.
	The contents of the manual have also been reorganized somewhat to conform
	with present Computer Group practice for board manuals.

June 2001	All data referring to the VME CSR Bit Set Register (VCSR_SET) and VME
	CSR Bit Clear Register (VCSR_CLR) has been deleted. These registers of the
	Universe II are unavailable for implementation as intended by the MVME
	materials and the Universe II User Manual.

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Motorola MVME2300 Series manual Summary of Changes, Date Description of Change

Contents

Programmer’s Reference Guide MVME2300 Series VME Processor ModulePage Safety Summary Flammability InstructionsCE Notice European Community Limited and Restricted Rights Legend Contents Raven PCI Bridge Asic Page Page Falcon ECC Memory Controller Chip Set Universe VMEbus to PCI Chip Chapter Page List of Figures Page List of Tables Xviii Model Memory Processor 16MB ECC Dram32MB ECC Dram 64MB ECC DramSummary of Changes Date Description of ChangeOverview of Contents Comments and SuggestionsConventions Used in This Manual BoldEnter, Return or CR CtrlXxiii Xxiv Introduction OverviewSummary of Features Features MVME2300 SeriesFeature MVME2300 ECC DramSystem Block Diagram Scsa I/OBoard Description and Memory Maps MVME2300 Series System Block Diagram Front Panel Functional DescriptionVMEbus Interface Programming Model PCI interfaceProcessor Memory Maps P2 I/ODefault Processor Memory Map Processor Address Size Definition Start EndProcessor Chrp Memory Map Chrp Memory Map ExampleRaven MPC Register Values for Chrp Memory Map Address Register Name Register ValueBfff Ffff Processor Prep Memory MapPrep Memory Map Example PCI Configuration Access Raven MPC Register Values for Prep Memory MapDefault PCI Memory Map PCI Memory MapsPCI Chrp Memory Map PCI Address Size Definition Start EndFC03 Ffff Universe PCI Register Values for Chrp Memory Map Configuration Register Value Address Offset Register NameRaven PCI Register Values for Chrp Memory Map PCI Prep Memory Map 10. PCI Prep Memory Map38FF Ffff 39FE Ffff39FF Ffff 3AFE Ffff11. Raven PCI Register Values for Prep Memory Map 12. Universe PCI Register Values for Prep Memory Map VMEbus Mapping VMEbus Master MapVMEbus Slave Map VMEbus Slave Mapping VSI0CTL VSI0BSVSI0BD VSI0TOVMEbus Address Size Chrp Map Prep Map Range Mode Falcon-Controlled System Registers14. VMEbus Slave Map Example 15. System Register SummarySystem Configuration Register Syscr System Configuration Register $FEF80400$FD Sysclk Value System Clock Speed PCI Clock SpeedP0/1STAT Value Processor 0/1 Present External In-line Cache Memory Configuration Register Memcr Memory Configuration Register $FEF80404MSIZE01 MSIZE01 Total Memory On BoardL2TYPE03 MSPD01RA/BTYP02 L2PLL03 FLSHP02System External Cache Control Register Sxccr PLL Value SizeProcessor 0 External Cache Control Register P0XCCR Processor 1 External Cache Control Register P1XCCRCPU Control Register CPU Control Register $FEF88300Access Registers ISA Local Resource BusW83C553 PIB Registers UartNVRAM/RTC and Watchdog Timer Registers General-Purpose Readable JumpersModule Configuration and Status Registers 17. M48T59/559 Access Registers18. Module Configuration and Status Registers PCI I/O Address FunctionCPU Configuration Register Old CPU Configuration Register $FE000800Cputype SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0Pcixp PMC2P PMC1P Vmep Lanp Base Module Feature RegisterBase Module Feature Register Offset $0802 Base Module Status Register Bmsr BasetypeBase Module Status Register Offset $0803 BasetypeVME Registers Seven-Segment Display RegisterSegment Display Register Offset $08C0 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD019. VME Registers LM/SIG Control RegisterSETSIG1 SETSIG0LM/SIG Status Register Board Description and Memory Maps Location Monitor Upper Base Address Register Location Monitor Lower Base Address RegisterLocation Monitor Upper Base Address Register Offset $1002 Location Monitor Lower Base Address Register Offset $1003Semaphore Register Semaphore Register 1 Offset $1004SEM1 Semaphore Register 2 Offset $1005Emulated Z8536 CIO Registers and Port Pins 20. Emulated Z8536 Access RegistersVME Geographical Address Register Vgar Emulated Z8536 Registers21. Z8536 CIO Port Pin Assignments Z8536 CIO Port PinsPort Signal Direction Descriptions Pin Name PC3 BASETYP1 ISA DMA ChannelsPC2 BASETYP0 Page Function Features FeaturesFeatures of the Raven Asic Block Diagram Raven Block Diagram MPC Bus Interface MPC Address MappingMPC-to-PCI Address Decoding MPC to PCI Address Translation MPC SlaveCommand Types MPC Slave Response MPC Transfer Type Transaction EncodingMPC Write Posting MPC MasterMPC Transfer Type MPC Transfer Size TT0-TT4 PCI Command CodeMPC Transfer Types MPC Bus Timer MPC ArbiterConfiguration Registers PCI Address MappingMPC Bus Address Space PCI to MPC Address DecodingRavenMPIC Control Registers Decoder PriorityPCI Slave Command Types Command Types PCI Slave ResponseCommand Type Slave Response? AddressingExclusive Access Device SelectionTarget-Initiated Termination Fast Back-to-Back TransactionsParity Cache SupportPCI Write Posting PCI MasterPCI Master Command Codes PCI CommandEntity Addressed Transfer TypeCombining, Merging, and Collapsing Master Initiated TerminationAddress/Data Stepping ArbitrationArbitration Latency PCI Cycle Type Generating PCI CyclesGenerating PCI Memory and I/O Cycles Generating PCI Configuration Cycles PCI Spread I/O Address TranslationFunctional Description Generating PCI Special Cycles Device Number Address BitGenerating PCI Interrupt Acknowledge Cycles When MPC Devices are Big-EndianEndian Conversion Big- to Little-Endian Data Swap When MPC Devices are Little-Endian Raven Registers and Endian ModeAddress Modification for Little-Endian Transfers Data Address Length Bytes ModificationError Handling Error Status Error Address Attributes Transaction OrderingSMA PerrRaven Registers MPC RegistersRaven MPC Register Map Devid Vendor ID/Device ID RegistersVenid General Control-Status/Feature Registers Revision ID RegisterRevid Revision ID. Identifies the Raven revision level. ThisFlbrd BhogMarb MpicCurrent MPC Data Bus Master MIDxFeat Prescaler Adjust Register Operation Reset $00Operation Reset $00 $B4 MPC Arbiter Control RegisterMPC Error Enable Register MatomSmam RtamMatoi PerriMato MPC Error Status RegisterOVF Writing it to a 0 has no effect. When the Smam bit SMAPCI transaction. The bit may be cleared by writing it to a RTAMPC Error Attribute Register Merat Which originated the transfer in which the error occurredRegister TTxDesignates a selected byte Operation Reset $0000 PCI Interrupt Acknowledge RegisterPiack Address $FEFF0030 Bit NameOperation Reset $8000 $8080 StartEND MPC Slave Address 3 RegisterMPC Slave Offset/Attribute 0,1 and 2 Registers MSOFFxREN WENMSOFF3 WpenIOM Cycles. When clear, the corresponding MPC slave will PCI RegistersRaven PCI Configuration Register Map $0C$18 $7F $8COperation Reset $4801 $1057 Raven PCI I/O Register Map$CF8 Offset $00 Bit NamePCI Command/ Status Registers Dpar SeltimSigta RcvtaRevision ID/ Class Code Registers ClassBase Register SpaceRES IobaIO/MEM PREBe compared with the upper 16 bits of the incoming PCI To access MPC bus resources. The value of this field willPCI Slave Address 0,1,2 and 3 Registers PCI Slave Attribute/ Offset 0,1,2 and 3 Registers INVTransfer type code which specifies the current transaction GBLConceptual perspective from the PCI bus Configaddress RegisterPerspective from the MPC bus in Big-Endian mode Perspective from the MPC bus in Little-Endian mode REGFUN DEVBUS EN EnableConfigdata Register Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation Reset Data ‘B’ Data ‘C’ Data ‘D’ Operation ResetArchitecture FeaturesRaven Interrupt Controller Processor’s Current Task Priority Readability of CSRInterrupt Source Priority Nesting of Interrupt Events Spurious Vector GenerationInterprocessor Interrupts IPI CompatibilityRaven-Detected Errors TimersInterrupt Delivery Modes Block Diagram Description Raven Interrupt ControllerInterrupt Selector is Program-Visible RegistersInterrupt Pending Register IPR Interrupt Router In-Service Register ISRInterrupt Request Register IRR Raven PCI Bridge Asic Mpic Registers RavenMPIC Registers10. RavenMPIC Register Map Off$011E0 $010E0$010F0 $100E0 $100F0$101E0 $101F0VID Feature Reporting RegisterNcpu Global Configuration Register Offset $01020 Bit NameProcessor 1. Writing a 1 to P1 will assert the Soft Reset Vendor Identification RegisterSTP Processor Init RegisterIPI Vector/Priority Registers MaskACT PriorSpurious Vector Register Interrupt Acknowledge register is read during a spuriousVector fetch Offset $010E0 Bit NameTimer Current Count Registers Timer Base Count RegistersCount Inhibit. Setting this bit to 1 inhibits counting for This timer. Setting the bit to 0 allows counting to proceedBase Count. This field contains the 31-bit count for this Bit transitions from a 1 to a 0, the value is copied intoTimer Destination Registers Setting this bit to a 0 enables active low or negative edge External Source Vector/Priority RegistersPOL SenseExternal Source Destination Registers Raven-Detected Errors Vector/Priority Register Offset $10200 Bit NameRaven-Detected Errors Destination Register Offset $10210 Bit NameOffset Processor $20080 $21080 Bit Name Zero is assumed. Writing to this register signals the end Interrupt Acknowledge RegistersEnd-of-Interrupt Registers End Of Interrupt. There is one EOI register perExternal Interrupt Service Programming NotesReset State Dynamically Changing I/O Interrupt Configuration Interprocessor InterruptsEOI Register Interrupt Acknowledge RegisterMode Current Task Priority LevelArchitectural Notes Page Features of the Falcon Chip Set DramBlock Diagrams Falcon Pair Used with Dram in a SystemFalcon Internal Data Paths Simplified Overall Dram Connections Four-beat Reads/Writes Bit Ordering ConventionPerformance Single-beat Reads/Writes Dram SpeedsPowerPC 60x Bus to Dram Access Timing 70ns Page Devices Clock Periods Required For Total Access Type2nd 3rd 4th BeatPowerPC 60x Bus to Dram Access Timing 60ns Page Devices 2nd 3rd 4th Clocks BeatPowerPC Bus to Dram Access Timing 50ns Hyper Devices ROM/Flash Speeds PowerPC 60x Bus Interface Responding to Address TransfersCompleting Data Transfers Cache CoherencyCycle Types Cache Coherency RestrictionsL2 Cache Support Error Reporting Single-BitROM/Flash Interface Error LoggingDram Tester Functional Description $XXFFFFF8 $7FFFFC $XXFFFFF9 $7FFFFD$XXFFFFFA $7FFFFE $XXFFFFFB $7FFFFF$X3FFFFF0 $7FFFFE $X3FFFFF1 $7FFFFE$X3FFFFF2 $7FFFFE $X3FFFFF3 $7FFFFERefresh/Scrub Blocks a and/or B Present, Blocks C and D Not PresentBlocks a and/or B Present, Blocks C and/or D Present Chip Defaults Dram ArbitrationCSR Architecture CSR AccessesExternal Register Set Data Path for Reads from the Falcon Internal CSRs Data Path for Writes to the Falcon Internal CSRs Memory Map for Byte Reads to CSR 1906 Memory Map for 4-Byte Reads to CSR Register Summary Detailed Register Bit Descriptions10. Register Summary Programming Model Test D3 Lower 32 BitsVendor/Device Register Address $FEF80000 Bit NameRevision ID/ General Control Register Read Zero Read onlyRam spd0, ram spd1 Dram Speed Dram Type Ram spd0,ram spd111. ram spd1,ram spd0 and Dram Type Ram a/b/c/d siz0-2 Dram Attributes RegisterRam a/b/c/d en BlockA/B/C/D Configurations Ram a/b/c/d Block Size Devices Used Technology Comments0MB SIMM/DIMMDram Base Register RAM A/B/C/D BaseCLK Frequency Register CLK FrequencyECC Control Register RefdisRwcb Read Zero11707.00 Falcon ECC Memory Controller Chip Set Tien SienMien MckenElog Esen EmbtError Address Register Address $FEF80038 Bit NameRtest0,rtest1,rtest2 Test Mode selected 13. rtest EncodingsRefresh/Scrub Address Register Address $FEF80048 Bit NameROM a Base 1Mbyte of Block a also appears at $FFF0000014. ROM Block a Size Encoding 15. romarv and rombrv EncodingRom a siz Block Size 1MB16. Read/Write to ROM/Flash Cycle Transfer Alignment Romx64 Romxwe Falcon Response1Mbyte of Block B also appears at $FFF00000 ROM B Base/Size RegisterROM B Base 17. ROM Block B Size Encoding Rom b siz Block SizeDram Tester Control Registers Bit CounterCTR32 is a 32-bit, free-running counter that increments Has been programmed properly. Notice that CTR32 isAddress $FEF80500 Bit Name Power-Up Reset Status RegisterAddress $FEF80400 Bit Name External Register Set Address $FEF88000 $FEF8FFF8 Bit NameParity Checking on the PowerPC Bus Software ConsiderationsProgramming ROM/Flash Devices Writing to the Control RegistersSizing Dram Software Considerations 19. PowerPC 60x Address to Dram Address Mappings 18. Sizing Addresses1024MB 256MB 128MB 64MB 32MB 16MB ROWBit Syndrome 20. Syndrome Codes Ordered by Bit in ErrorECC Codes 20. Syndrome Codes Ordered by Bit in Error 21. Single-Bit Errors Ordered by Syndrome Code $AF $CF $EF10. PowerPC Data to Dram Data Correspondence Data Paths22. PowerPC Data to Dram Data Mapping Page Universe VMEbus to PCI Chip Features of the Universe Asic − BLT, ADOH, RMW, LockBlock Diagram Architectural Diagram for the Universe Universe as VMEbus SlavePCI Bus Interface Universe as VMEbus MasterInterrupter Universe as PCI Slave Universe as PCI MasterDMA Controller VMEbus Interrupt HandlingUniverse Control and Status Registers Ucsr Ucsr Access Mechanisms Universe Register Map Offset Register Name LSI2BS LSI2BDLSI2TO LSI3BSDcpp DgcsDllue LintenVSI0BD F0C VSI1BS F1CVSI2CTL F2C VSI2BSUniverse Chip Problems after PCI Reset DescriptionWorkarounds MethodExample 1 MVME2600 Series Board Exhibits PCI Reset Problem ExamplesExample 2 MVME3600 Series Board Acts Differently Run the init code and the LSI0 registers become Example 3 Universe Chip is Checked at Tundra Universe VMEbus to PCI Chip PCI Arbitration PCI Arbitration AssignmentsPci Bus Request PCI Masters PIBInterrupt Handling MVME2300 Series Interrupt ArchitectureRavenMPIC RavenMPIC Interrupt AssignmentsEdge Polarity Interrupt Source LevelIRQ15 InterruptsIRQ14 PIB Interrupt Handler Block Diagram PIB PCI/ISA Interrupt Assignments EdgeISA DMA Channels Exceptions Sources of ResetReset switch Soft Reset Reset Sources and Devices AffectedSources of Reset Devices AffectedCause Action Error Notification and HandlingError Notification and Handling Endian Issues Big-Endian ModeLittle-Endian Mode Processor/Memory Domain Role of the Raven AsicPCI Domain PCI/EthernetPCI-Graphics Role of the Universe AsicVMEbus Domain ROM/Flash Initialization ROM/Flash Bank DefaultDefault Mapping for FFF00000-FFFFFFFF Page Motorola Computer Group Documents Document Title Publication NumberManufacturers’ Documents Document Title and Source Publication NumberMPCFPE/AD EK-DE500-OMIEC 821 BUS Related SpecificationsANSI/IEEE TIA/EIA-232 MPR-PPC-RPU-02Isbn Page Glossary O S S a R Y Enhanced Integrated Drive Electronics. An improved version PCI. Used in the reference platform specification. IBM Computers developed by the IBM Corporation. PowerPC is IBMSignal Computing System Architecture. a hardware model for See 10base-2 Page Index PCI 1-13 processor IN-3 MPC PCIIN-5 Configaddress 2-56CONFIGDATA IN-7 IN-8