Motorola MVME2300 Series manual Cache Coherency Restrictions, L2 Cache Support, Cycle Types

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Falcon ECC Memory Controller Chip Set

Cache Coherency Restrictions

The PowerPC 60x GBL_ signal must not be asserted in the CSR areas.

L2 Cache Support

The Falcon pair provides support for a look-aside L2 cache by implementing a hold-off input, L2CLM_. On cycles that select the Falcon pair, the Falcon pair samples L2CLM_ on the second rising edge of CLOCK after the assertion of TS_. If L2CLM_ is high, the Falcon pair responds normally to the cycle. If it is low, the Falcon pair ignores the cycle.

Note The MVME2300 series boards have no L2 cache.

ECC

The Falcon pair performs single-bit error correction and double-bit error detection for DRAM. (No checking is provided for ROM/Flash.) The 64- bit wide PowerPC 60x data bus is divided into upper (DH0-DH31) and lower (DL0-DL31) halves. Each half is routed through a Falcon which multiplexes it with half of the DRAM data bus. Each Falcon connects to 64 DRAM data-bits and to 8 DRAM check-bits. The total DRAM array width is 144 bits (2× [64+8]).

Cycle Types

To support ECC, the Falcon pair always deals with DRAM using full width (144-bit) accesses. When the PowerPC 60x bus master requests any size read of DRAM, the Falcon pair reads 144 bits at least once. When the PowerPC 60x bus master requests a four-beat write to DRAM, the Falcon pair writes all 144 bits twice. When the PowerPC 60x bus master requests a single-beat write to DRAM, the Falcon pair performs a 144-bit wide read cycle to DRAM, merges in the appropriate PowerPC 60x bus write data, and writes 144 bits back to DRAM.

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