Motorola MVME2300 Series manual MPC Write Posting, MPC Master

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Raven PCI Bridge ASIC

MPC Write Posting

The MPC write FIFO stores up to eight data beats in any combination of single- and four-beat (burst) transactions. If write-posting is enabled, Raven stores the data necessary to complete an MPC write transfer to the PCI bus and immediately acknowledges the transaction on the MPC bus. This frees the MPC bus from waiting for the potentially long PCI arbitration and transfer. The MPC bus may be used for more useful work while the Raven manages the completion of the write-posted transaction on PCI.

All transactions will be completed on the PCI bus in the same order that they are completed on the MPC bus. A read or a compelled write transaction will force all previously issued write-posted transactions to be flushed from the FIFO. All write-posted transfers will be completed before a non-write-posted read or write is begun, to assure that all transfers are completed in the order issued. All write-posted transfers will also be completed before any access to the Raven’s registers is begun.

MPC Master

The MPC master will attempt to move data using burst transfers wherever possible. A 64-bit-by-16 entry FIFO is used to hold data between the PCI slave and the MPC master to ensure that optimum data throughput is maintained. While the PCI slave is filling the FIFO with one cache line worth of data, the MPC master can be moving another cache line worth onto the MPC bus. This will allow the PCI slave to receive long block transfers without stalling.

When programmed in “read ahead” mode (the RAEN bit in the PSATTx register is set) and the PCI slave receives a Memory Read Line or Memory Read Multiple command, the MPC master will fetch data in bursts and store it in the FIFO. The contents of the FIFO will then be used to attempt to satisfy the data requirements for the remainder of the PCI block transaction. If the data requested is not in the FIFO, the MPC master will read another cache line. The contents of the FIFO are “invalidated” at the end of each PCI block transaction.

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