Motorola MVME2300 Series manual Readability of CSR, Interrupt Source Priority

Raven Interrupt Controller

The RavenMPIC receives interrupt inputs from:

❏16 external sources

❏Four interprocessor sources

❏Four timer sources

❏One Raven internal error detection source

Externally sourced interrupts 1 through 15 have two modes of activation: low level or active high positive edge. External interrupt 0 can be either level- or edge-activated with either polarity. The Interprocessor and timer interrupts are event-activated.

Readability of CSR

Unless explicitly specified, all registers are readable and return the last value written. The exceptions are the IPI dispatch registers and the EOI registers which return 0s on reads, the interrupt source ACT bit which returns current interrupt source status, the interrupt acknowledge register which returns the vector of the highest-priority currently pending interrupt, and reserved bits which return 0s. The interrupt acknowledge register is also the only register which exhibits any read side-effects.

Interrupt Source Priority

Each interrupt source is assigned a priority value in the range from 0 to 15, where 15 is the highest priority level. For delivery of an interrupt to take place, the priority of the source must be greater than that of the destination processor. Therefore, setting a source priority to zero inhibits that interrupt.

Processor’s Current Task Priority

Each processor has a task priority register which is set by system software to indicate the relative importance of the task running on that processor. The processor will not receive interrupts with a priority level equal to or lower than its current task priority. Therefore, setting the current task priority to 15 prohibits the delivery of all interrupts to the associated processor.

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