Motorola MVME2300 Series manual Features of the Raven Asic, Function Features

Raven PCI Bridge ASIC

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Introduction

This chapter describes the architecture and usage of the Raven ASIC, a PowerPC-to-PCI-Local-Bus bridge controller chip. The Raven is intended to provide PowerPC 60x (MPC60x) compliant devices access to devices residing on the PCI Local Bus. In the remainder of this chapter, the MPC60x bus is referred to as the "MPC bus" and the PCI Local Bus is referred to as "PCI". PCI is a high-performance 32-bit or 64-bit, burst mode, synchronous bus capable of transfer rates of 132 MB/sec in 32-bit mode or 264 MB/sec in 64-bit mode using a 33MHz clock.

Features

The following table summarizes the characteristics of the Raven ASIC.

	Table 2-1. Features of the Raven ASIC
Function	Features
MPC Bus Interface	Direct interface to MPC603 or MPC604 processors
	64-bit data bus, 32-bit address bus
	Four independent software-programmable slave map decoders
	Multi-level write-post FIFO for writes to PCI
	Support for MPC bus clock speeds up to 66MHz
	Selectable big- or little-endian operation
	3.3V signal levels
PCI Interface	Fully PCI Rev. 2.0 compliant
	32-bit or 64-bit address/data bus
	Support for accesses to all four PCI address spaces
	Single-level write-posting buffers for writes to the MPC bus
	Read-ahead buffer for reads from the MPC bus
	Four independent software-programmable slave map decoders

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