Architectural Diagram for the Universe | Motorola MVME2300 Series

Universe (VMEbus to PCI) Chip

4

PCI

BUS

		DMA Channel
	PCI Bus	DMA bidirectional FIFO
	PCI Bus
	Interface
		VMEbus Slave Channel
	PCI	posted writes FIFO
	PCI	prefetch read FIFO
	Master	prefetch read FIFO
	Master	coupled read
		coupled read
		PCI Bus Slave Channel
	PCI	posted writes FIFO
	Slave	coupled read logic
		Interrupt Channel
	PCI	Interrupt Handler
	Interrupts	Interrupter

	VMEbus
	Interface
	VME
	Slave
	VME	VMEbus
	Master	VMEbus
	Master
	VME
	Interrupts

Register Channel

1894 9609

Figure 4-1. Architectural Diagram for the Universe

VMEbus Interface

This section examines the Universe ASIC’s VMEbus interface function, from the standpoint of the Universe as VMEbus slave as well as VMEbus master.

Universe as VMEbus Slave

The Universe VME Slave channel accepts all of the addressing and data transfer modes documented in the VME64 specification (except A64 and those intended to support 3U applications, that is, A40 and MD32). Incoming write transactions from the VMEbus may be treated as either coupled or posted, depending upon the programming of the VMEbus slave image. (Refer to VME Slave Images in the Universe User Manual.) With posted write transactions, data is written to a Posted Write Receive FIFO (RXFIFO), and the VMEbus master receives data acknowledgment from

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Motorola MVME2300 Series manual Architectural Diagram for the Universe, Universe as VMEbus Slave

Contents

Programmer’s Reference Guide MVME2300 Series VME Processor ModulePage Safety Summary Flammability Instructions CE Notice European Community Limited and Restricted Rights Legend Contents Raven PCI Bridge Asic Page Page Falcon ECC Memory Controller Chip Set Universe VMEbus to PCI Chip Chapter Page List of Figures Page List of Tables Xviii Model Memory Processor 16MB ECC Dram32MB ECC Dram 64MB ECC Dram Summary of Changes Date Description of Change Overview of Contents Comments and Suggestions Conventions Used in This Manual BoldEnter, Return or CR Ctrl Xxiii Xxiv Introduction Overview Summary of Features Features MVME2300 SeriesFeature MVME2300 ECC Dram System Block Diagram Scsa I/O Board Description and Memory Maps MVME2300 Series System Block Diagram Functional Description VMEbus InterfaceFront Panel Programming Model PCI interfaceProcessor Memory Maps P2 I/O Default Processor Memory Map Processor Address Size Definition Start End Processor Chrp Memory Map Chrp Memory Map Example Raven MPC Register Values for Chrp Memory Map Address Register Name Register Value Processor Prep Memory Map Prep Memory Map ExampleBfff Ffff PCI Configuration Access Raven MPC Register Values for Prep Memory Map Default PCI Memory Map PCI Memory MapsPCI Chrp Memory Map PCI Address Size Definition Start End FC03 Ffff Configuration Register Value Address Offset Register Name Raven PCI Register Values for Chrp Memory MapUniverse PCI Register Values for Chrp Memory Map PCI Prep Memory Map 10. PCI Prep Memory Map 38FF Ffff 39FE Ffff39FF Ffff 3AFE Ffff 11. Raven PCI Register Values for Prep Memory Map 12. Universe PCI Register Values for Prep Memory Map VMEbus Mapping VMEbus Master Map VMEbus Slave Map VMEbus Slave Mapping VSI0CTL VSI0BSVSI0BD VSI0TO VMEbus Address Size Chrp Map Prep Map Range Mode Falcon-Controlled System Registers14. VMEbus Slave Map Example 15. System Register Summary System Configuration Register Syscr System Configuration Register $FEF80400$FD Sysclk Value System Clock Speed PCI Clock Speed P0/1STAT Value Processor 0/1 Present External In-line Cache Memory Configuration Register Memcr Memory Configuration Register $FEF80404MSIZE01 MSIZE01 Total Memory On Board MSPD01 RA/BTYP02L2TYPE03 L2PLL03 FLSHP02System External Cache Control Register Sxccr PLL Value Size Processor 0 External Cache Control Register P0XCCR Processor 1 External Cache Control Register P1XCCRCPU Control Register CPU Control Register $FEF88300 Access Registers ISA Local Resource BusW83C553 PIB Registers Uart NVRAM/RTC and Watchdog Timer Registers General-Purpose Readable Jumpers Module Configuration and Status Registers 17. M48T59/559 Access Registers18. Module Configuration and Status Registers PCI I/O Address Function CPU Configuration Register Old CPU Configuration Register $FE000800Cputype SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Base Module Feature Register Base Module Feature Register Offset $0802Pcixp PMC2P PMC1P Vmep Lanp Base Module Status Register Bmsr BasetypeBase Module Status Register Offset $0803 Basetype VME Registers Seven-Segment Display RegisterSegment Display Register Offset $08C0 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 19. VME Registers LM/SIG Control RegisterSETSIG1 SETSIG0 LM/SIG Status Register Board Description and Memory Maps Location Monitor Upper Base Address Register Location Monitor Lower Base Address RegisterLocation Monitor Upper Base Address Register Offset $1002 Location Monitor Lower Base Address Register Offset $1003 Semaphore Register Semaphore Register 1 Offset $1004SEM1 Semaphore Register 2 Offset $1005 Emulated Z8536 CIO Registers and Port Pins 20. Emulated Z8536 Access RegistersVME Geographical Address Register Vgar Emulated Z8536 Registers Z8536 CIO Port Pins Port Signal Direction Descriptions Pin Name21. Z8536 CIO Port Pin Assignments ISA DMA Channels PC2 BASETYP0PC3 BASETYP1 Page Features Features of the Raven AsicFunction Features Block Diagram Raven Block Diagram MPC Bus Interface MPC Address Mapping MPC-to-PCI Address Decoding MPC to PCI Address Translation MPC Slave Command Types MPC Slave Response MPC Transfer Type Transaction Encoding MPC Write Posting MPC Master PCI Command Code MPC Transfer TypesMPC Transfer Type MPC Transfer Size TT0-TT4 MPC Bus Timer MPC Arbiter Configuration Registers PCI Address Mapping MPC Bus Address Space PCI to MPC Address Decoding RavenMPIC Control Registers Decoder Priority PCI Slave Command Types Command Types PCI Slave ResponseCommand Type Slave Response? Addressing Exclusive Access Device SelectionTarget-Initiated Termination Fast Back-to-Back Transactions Parity Cache SupportPCI Write Posting PCI Master PCI Master Command Codes PCI CommandEntity Addressed Transfer Type Combining, Merging, and Collapsing Master Initiated Termination Arbitration Arbitration LatencyAddress/Data Stepping Generating PCI Cycles Generating PCI Memory and I/O CyclesPCI Cycle Type Generating PCI Configuration Cycles PCI Spread I/O Address Translation Functional Description Generating PCI Special Cycles Device Number Address Bit When MPC Devices are Big-Endian Endian ConversionGenerating PCI Interrupt Acknowledge Cycles Big- to Little-Endian Data Swap When MPC Devices are Little-Endian Raven Registers and Endian ModeAddress Modification for Little-Endian Transfers Data Address Length Bytes Modification Error Handling Error Status Error Address Attributes Transaction OrderingSMA Perr Raven Registers MPC Registers Raven MPC Register Map Vendor ID/Device ID Registers VenidDevid General Control-Status/Feature Registers Revision ID RegisterRevid Revision ID. Identifies the Raven revision level. This Flbrd BhogMarb Mpic MIDx FeatCurrent MPC Data Bus Master Prescaler Adjust Register Operation Reset $00Operation Reset $00 $B4 MPC Arbiter Control Register MPC Error Enable Register Matom Smam RtamMatoi Perri MPC Error Status Register OVFMato Writing it to a 0 has no effect. When the Smam bit SMAPCI transaction. The bit may be cleared by writing it to a RTA MPC Error Attribute Register Merat Which originated the transfer in which the error occurredRegister TTx Designates a selected byte Operation Reset $0000 PCI Interrupt Acknowledge RegisterPiack Address $FEFF0030 Bit Name Operation Reset $8000 $8080 StartEND MPC Slave Address 3 Register MPC Slave Offset/Attribute 0,1 and 2 Registers MSOFFxREN WEN Wpen IOMMSOFF3 Cycles. When clear, the corresponding MPC slave will PCI Registers Raven PCI Configuration Register Map $0C$18 $7F $8C Operation Reset $4801 $1057 Raven PCI I/O Register Map$CF8 Offset $00 Bit Name PCI Command/ Status Registers Dpar SeltimSigta Rcvta Revision ID/ Class Code Registers ClassBase Register Space RES IobaIO/MEM PRE To access MPC bus resources. The value of this field will PCI Slave Address 0,1,2 and 3 RegistersBe compared with the upper 16 bits of the incoming PCI PCI Slave Attribute/ Offset 0,1,2 and 3 Registers INVTransfer type code which specifies the current transaction GBL Configaddress Register Perspective from the MPC bus in Big-Endian modeConceptual perspective from the PCI bus Perspective from the MPC bus in Little-Endian mode REGFUN DEV EN Enable Configdata RegisterBUS Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation Reset Data ‘B’ Data ‘C’ Data ‘D’ Operation Reset Features Raven Interrupt ControllerArchitecture Readability of CSR Interrupt Source PriorityProcessor’s Current Task Priority Nesting of Interrupt Events Spurious Vector GenerationInterprocessor Interrupts IPI Compatibility Raven-Detected Errors Timers Interrupt Delivery Modes Block Diagram Description Raven Interrupt Controller Program-Visible Registers Interrupt Pending Register IPRInterrupt Selector is In-Service Register ISR Interrupt Request Register IRRInterrupt Router Raven PCI Bridge Asic Mpic Registers RavenMPIC Registers10. RavenMPIC Register Map Off $010E0 $010F0$011E0 $100E0 $100F0 $101E0 $101F0 Feature Reporting Register NcpuVID Global Configuration Register Offset $01020 Bit Name Processor 1. Writing a 1 to P1 will assert the Soft Reset Vendor Identification RegisterSTP Processor Init Register IPI Vector/Priority Registers MaskACT Prior Spurious Vector Register Interrupt Acknowledge register is read during a spuriousVector fetch Offset $010E0 Bit Name Timer Current Count Registers Timer Base Count Registers Count Inhibit. Setting this bit to 1 inhibits counting for This timer. Setting the bit to 0 allows counting to proceedBase Count. This field contains the 31-bit count for this Bit transitions from a 1 to a 0, the value is copied into Timer Destination Registers Setting this bit to a 0 enables active low or negative edge External Source Vector/Priority RegistersPOL Sense External Source Destination Registers Raven-Detected Errors Vector/Priority Register Offset $10200 Bit Name Raven-Detected Errors Destination Register Offset $10210 Bit Name Offset Processor $20080 $21080 Bit Name Zero is assumed. Writing to this register signals the end Interrupt Acknowledge RegistersEnd-of-Interrupt Registers End Of Interrupt. There is one EOI register per External Interrupt Service Programming Notes Reset State Dynamically Changing I/O Interrupt Configuration Interprocessor Interrupts EOI Register Interrupt Acknowledge RegisterMode Current Task Priority Level Architectural Notes Page Features of the Falcon Chip Set Dram Block Diagrams Falcon Pair Used with Dram in a System Falcon Internal Data Paths Simplified Overall Dram Connections Bit Ordering Convention PerformanceFour-beat Reads/Writes Single-beat Reads/Writes Dram Speeds PowerPC 60x Bus to Dram Access Timing 70ns Page Devices Clock Periods Required For Total Access Type2nd 3rd 4th Beat PowerPC 60x Bus to Dram Access Timing 60ns Page Devices 2nd 3rd 4th Clocks Beat PowerPC Bus to Dram Access Timing 50ns Hyper Devices ROM/Flash Speeds PowerPC 60x Bus Interface Responding to Address TransfersCompleting Data Transfers Cache Coherency Cache Coherency Restrictions L2 Cache SupportCycle Types Error Reporting Single-Bit Error Logging Dram TesterROM/Flash Interface Functional Description $XXFFFFF8 $7FFFFC $XXFFFFF9 $7FFFFD$XXFFFFFA $7FFFFE $XXFFFFFB $7FFFFF $X3FFFFF0 $7FFFFE $X3FFFFF1 $7FFFFE$X3FFFFF2 $7FFFFE $X3FFFFF3 $7FFFFE Refresh/Scrub Blocks a and/or B Present, Blocks C and D Not Present Blocks a and/or B Present, Blocks C and/or D Present Chip Defaults Dram Arbitration CSR Accesses External Register SetCSR Architecture Data Path for Reads from the Falcon Internal CSRs Data Path for Writes to the Falcon Internal CSRs Memory Map for Byte Reads to CSR 1906 Memory Map for 4-Byte Reads to CSR Register Summary Detailed Register Bit Descriptions 10. Register Summary Programming Model Test D3 Lower 32 Bits Vendor/Device Register Address $FEF80000 Bit Name Revision ID/ General Control Register Read Zero Read only Ram spd0,ram spd1 11. ram spd1,ram spd0 and Dram TypeRam spd0, ram spd1 Dram Speed Dram Type Dram Attributes Register Ram a/b/c/d enRam a/b/c/d siz0-2 BlockA/B/C/D Configurations Ram a/b/c/d Block Size Devices Used Technology Comments0MB SIMM/DIMM Dram Base Register RAM A/B/C/D BaseCLK Frequency Register CLK Frequency ECC Control Register RefdisRwcb Read Zero 11707.00 Falcon ECC Memory Controller Chip Set Tien SienMien Mcken Elog Esen Embt Error Address Register Address $FEF80038 Bit Name Rtest0,rtest1,rtest2 Test Mode selected 13. rtest Encodings Refresh/Scrub Address Register Address $FEF80048 Bit Name ROM a Base 1Mbyte of Block a also appears at $FFF00000 14. ROM Block a Size Encoding 15. romarv and rombrv EncodingRom a siz Block Size 1MB 16. Read/Write to ROM/Flash Cycle Transfer Alignment Romx64 Romxwe Falcon Response ROM B Base/Size Register ROM B Base1Mbyte of Block B also appears at $FFF00000 17. ROM Block B Size Encoding Rom b siz Block Size Dram Tester Control Registers Bit CounterCTR32 is a 32-bit, free-running counter that increments Has been programmed properly. Notice that CTR32 is Power-Up Reset Status Register Address $FEF80400 Bit NameAddress $FEF80500 Bit Name External Register Set Address $FEF88000 $FEF8FFF8 Bit Name Parity Checking on the PowerPC Bus Software ConsiderationsProgramming ROM/Flash Devices Writing to the Control Registers Sizing Dram Software Considerations 19. PowerPC 60x Address to Dram Address Mappings 18. Sizing Addresses1024MB 256MB 128MB 64MB 32MB 16MB ROW 20. Syndrome Codes Ordered by Bit in Error ECC CodesBit Syndrome 20. Syndrome Codes Ordered by Bit in Error 21. Single-Bit Errors Ordered by Syndrome Code $AF $CF $EF 10. PowerPC Data to Dram Data Correspondence Data Paths 22. PowerPC Data to Dram Data Mapping Page Universe VMEbus to PCI Chip Features of the Universe Asic − BLT, ADOH, RMW, Lock Block Diagram Architectural Diagram for the Universe Universe as VMEbus Slave PCI Bus Interface Universe as VMEbus Master Interrupter Universe as PCI Slave Universe as PCI Master DMA Controller VMEbus Interrupt Handling Universe Control and Status Registers Ucsr Ucsr Access Mechanisms Universe Register Map Offset Register Name LSI2BS LSI2BDLSI2TO LSI3BS Dcpp DgcsDllue Linten VSI0BD F0C VSI1BS F1CVSI2CTL F2C VSI2BS Universe Chip Problems after PCI Reset Description Workarounds Method Example 1 MVME2600 Series Board Exhibits PCI Reset Problem Examples Example 2 MVME3600 Series Board Acts Differently Run the init code and the LSI0 registers become Example 3 Universe Chip is Checked at Tundra Universe VMEbus to PCI Chip PCI Arbitration PCI Arbitration AssignmentsPci Bus Request PCI Masters PIB Interrupt Handling MVME2300 Series Interrupt Architecture RavenMPIC RavenMPIC Interrupt AssignmentsEdge Polarity Interrupt Source Level Interrupts IRQ14IRQ15 PIB Interrupt Handler Block Diagram PIB PCI/ISA Interrupt Assignments Edge ISA DMA Channels Sources of Reset Reset switchExceptions Soft Reset Reset Sources and Devices AffectedSources of Reset Devices Affected Error Notification and Handling Error Notification and HandlingCause Action Endian Issues Big-Endian Mode Little-Endian Mode Processor/Memory Domain Role of the Raven AsicPCI Domain PCI/Ethernet Role of the Universe Asic VMEbus DomainPCI-Graphics ROM/Flash Bank Default Default Mapping for FFF00000-FFFFFFFFROM/Flash Initialization Page Motorola Computer Group Documents Document Title Publication Number Manufacturers’ Documents Document Title and Source Publication Number MPCFPE/AD EK-DE500-OM Related Specifications ANSI/IEEEIEC 821 BUS MPR-PPC-RPU-02 IsbnTIA/EIA-232 Page Glossary O S S a R Y Enhanced Integrated Drive Electronics. An improved version PCI. Used in the reference platform specification. IBM Computers developed by the IBM Corporation. PowerPC is IBM Signal Computing System Architecture. a hardware model for See 10base-2 Page Index PCI 1-13 processor IN-3 MPC PCI IN-5 Configaddress 2-56CONFIGDATA IN-7 IN-8