Motorola MVME2300 Series manual External Register Set, CSR Accesses, CSR Architecture

Programming Model

External Register Set

Each chip in the Falcon pair has an external register chip select pin which enables it to talk to an external set of registers. This interface is like the ROM/Flash interface but with less flexibility. It is intended for the system designer’s use in implementing general-purpose status/control signals. Refer to the Programming Model section of this chapter for a description of the external register set.

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CSR Accesses

An important part of the operation of a Falcon pair is that the value written to the internal control registers and SRAM in each of the two chips must be the same at all times. To facilitate this, writes to the pair itself are restricted to the upper Falcon only. When software writes to the upper Falcon, hardware in the two chips shifts this same value into the lower Falcon before the cycle completion is acknowledged. The shifting is done in holding registers such that the actual update of the control register happens on the same CLOCK cycle in both chips. Writes to the upper Falcon can be single-byte or 4-byte. Writes to the lower Falcon are ignored.

This duplicating of writes from upper to lower applies to the Falcon’s internal registers and SRAM only. No duplication is performed for writes to DRAM, ROM/Flash, or the External Register set.

Programming Model

The following sections describe the programming model for the Falcon chip set.

CSR Architecture

The CSR (Control/Status Register set) consists of the chip’s internal register set, its test SRAM, and its external register set. The base address of the CSR is hard coded to the address $FEF80000 (or $FEF90000 if the SIO pin is low at reset).

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