Motorola MVME2300 Series manual Dpar, Seltim, Sigta, Rcvta, Rcvma, Sigse, Rcvpe

	Raven Registers
DPAR	Data Parity Detected. This bit is set when three
	conditions are met: 1) the Raven asserted PERR∗ itself or
	observed PERR∗ asserted; 2) the Raven was the PCI
	master for the transfer in which the error occurred; 3) the
	PERR bit in the PCI Command register is set. This bit is
	cleared by writing it to 1; writing a 0 has no effect.
SELTIM	DEVSEL Timing. This field indicates that the Raven will
	always assert DEVSEL∗ as a ‘medium’ responder.
SIGTA	Signalled Target Abort. This bit is set by the PCI slave
	whenever it terminates a transaction with a target-abort.
	The bit is cleared by writing it to 1; writing a 0 has no
	effect.
RCVTA	Received Target Abort. This bit is set by the PCI master
	whenever its transaction is terminated by a target-abort.
	The bit is cleared by writing it to 1; writing a 0 has no
	effect.
RCVMA	Received Master Abort. This bit is set by the PCI master
	whenever its transaction (except for Special Cycles) is
	terminated by a master-abort. The bit is cleared by writing
	it to 1; writing a 0 has no effect.
SIGSE	Signaled System Error. This bit is set whenever the
	Raven asserts SERR∗. The bit is cleared by writing it to 1;
	writing a 0 has no effect.
RCVPE	Detected Parity Error. This bit is set whenever the
	Raven detects a parity error, even if parity error checking
	is disabled (see bit PERR in the PCI Command register).
	The bit is cleared by writing it to 1; writing a 0 has no
	effect.

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