Motorola MVME2300 Series manual Software Considerations, Parity Checking on the PowerPC Bus

Software Considerations

Software Considerations

This section contains information that may be helpful in making efficient use of the Falcon pair when programming.

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Parity Checking on the PowerPC Bus

The Falcon does not generate parity on the PowerPC address or data buses. Because of this, the appropriate registers in the MPC60x should be programmed to disable parity checking for the address bus and for the data bus.

Programming ROM/Flash Devices

Those who program devices to be controlled by the Falcon should make note of the address mapping that is shown in Table 3-8and in Table 3-9. When using eight-bit devices, for example, the code will be split so that every other four-byte segment goes in each device.

Writing to the Control Registers

Software should not change control register bits that affect DRAM operation while DRAM is being accessed. Because of pipelining, software should always make sure that the two accesses before and after the updating of critical bits are not DRAM accesses. A possible scenario for trouble would be to execute code out of DRAM while updating the critical DRAM control register bits. The preferred method is to be executing code out of ROM/Flash and avoiding DRAM accesses while updating these bits.

Since software has no way of controlling refresh accesses to DRAM, the hardware is designed so that updating control bits coincidentally with refreshes is not a problem. An exception to this is the ROW_ADDRESS and COL_ADDRESS bits. In any event, however, it is not intended that software write to these bits.

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