Motorola MVME2300 Series manual Falcon ECC Memory Controller Chip Set

8259 Mode	2-90
Current Task Priority Level	2-90
Architectural Notes	2-91
CHAPTER 3 Falcon ECC Memory Controller Chip Set
Introduction	3-1
Features	3-1
Block Diagrams	3-2
Functional Description	3-5
Bit Ordering Convention	3-5
Performance	3-5
Four-beat Reads/Writes	3-5
Single-beat Reads/Writes	3-6
DRAM Speeds	3-6
ROM/Flash Speeds	3-10
PowerPC 60x Bus Interface	3-11
Responding to Address Transfers	3-11
Completing Data Transfers	3-11
Cache Coherency	3-11
Cache Coherency Restrictions	3-12
L2 Cache Support	3-12
ECC	3-12
Cycle Types	3-12
Error Reporting	3-13
Error Logging	3-14
DRAM Tester	3-14
ROM/Flash Interface	3-14
Refresh/Scrub	3-18
Blocks A and/or B Present, Blocks C and D Not Present	3-18
Blocks A and/or B Present, Blocks C and/or D Present	3-19
DRAM Arbitration	3-20
Chip Defaults	3-20
External Register Set	3-21
CSR Accesses	3-21
Programming Model	3-21
CSR Architecture	3-21
Register Summary	3-27
Detailed Register Bit Descriptions	3-27
Vendor/Device Register	3-30
Revision ID/ General Control Register	3-31

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