Motorola MVME2300 Series manual MPC Transfer Types, PCI Command Code

Functional Description

Notes

1.Read-ahead mode should not be used when data coherency may be a problem, as there is no way to snoop all MPC bus transactions and invalidate the contents of the FIFO.

2.Accesses near the top of local memory with read-ahead mode enabled could cause the MPC master to perform reads beyond the top of local memory, which could produce an MPC bus timeout error.

The MPC bus transfer types generated by the MPC master depend on the PCI command code and the INV/GBL bits in the PSATTx registers. The GBL bit determines whether or not the GBL∗ signal is asserted for all portions of a transaction, and is fully independent of the PCI command code and INV bit. Table 2-3shows the relationship between PCI command codes and the INV bit.

Table 2-3. MPC Transfer Types

PCI Command Code	INV	MPC Transfer Type	MPC Transfer Size	TT0-TT4
Memory Read	0	Read	Burst/Single Beat	01010
Memory Read Multiple
Memory Read Line
Memory Read	1	Read With Intent to	Burst/Single Beat	01110
Memory Read Multiple		Modify
Memory Read Line
Memory Write	x	Write with Kill	Burst	00110
Memory Write and
Invalidate
Memory Write	x	Write with Flush	Single Beat	00010
Memory Write and
Invalidate

The MPC master incorporates an optional operating mode called Bus Hog. When Bus Hog is enabled, the MPC master will continually request the MPC bus for the entire duration of each PCI transfer. When Bus Hog is not

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