Programmer’s Reference Guide
MVME2300 Series VME Processor Module
Page
Safety Summary
Flammability
Instructions
CE Notice European Community
Limited and Restricted Rights Legend
Contents
Raven PCI Bridge Asic
Page
Page
Falcon ECC Memory Controller Chip Set
Universe VMEbus to PCI Chip
Chapter
Page
List of Figures
Page
List of Tables
Xviii
32MB ECC Dram
Model Memory Processor
16MB ECC Dram
64MB ECC Dram
Summary of Changes
Date Description of Change
Overview of Contents
Comments and Suggestions
Enter, Return or CR
Conventions Used in This Manual
Bold
Ctrl
Xxiii
Xxiv
Introduction
Overview
Feature MVME2300
Summary of Features
Features MVME2300 Series
ECC Dram
System Block Diagram
Scsa I/O
Board Description and Memory Maps
MVME2300 Series System Block Diagram
Front Panel
Functional Description
VMEbus Interface
Processor Memory Maps
Programming Model
PCI interface
P2 I/O
Default Processor Memory Map
Processor Address Size Definition Start End
Processor Chrp Memory Map
Chrp Memory Map Example
Raven MPC Register Values for Chrp Memory Map
Address Register Name Register Value
Bfff Ffff
Processor Prep Memory Map
Prep Memory Map Example
PCI Configuration Access
Raven MPC Register Values for Prep Memory Map
PCI Chrp Memory Map
Default PCI Memory Map
PCI Memory Maps
PCI Address Size Definition Start End
FC03 Ffff
Universe PCI Register Values for Chrp Memory Map
Configuration Register Value Address Offset Register Name
Raven PCI Register Values for Chrp Memory Map
PCI Prep Memory Map
10. PCI Prep Memory Map
39FF Ffff
38FF Ffff
39FE Ffff
3AFE Ffff
11. Raven PCI Register Values for Prep Memory Map
12. Universe PCI Register Values for Prep Memory Map
VMEbus Mapping
VMEbus Master Map
VMEbus Slave Map
VMEbus Slave Mapping
VSI0BD
VSI0CTL
VSI0BS
VSI0TO
14. VMEbus Slave Map Example
VMEbus Address Size Chrp Map Prep Map Range Mode
Falcon-Controlled System Registers
15. System Register Summary
$FD
System Configuration Register Syscr
System Configuration Register $FEF80400
Sysclk Value System Clock Speed PCI Clock Speed
P0/1STAT Value Processor 0/1 Present External In-line Cache
MSIZE01
Memory Configuration Register Memcr
Memory Configuration Register $FEF80404
MSIZE01 Total Memory On Board
L2TYPE03
MSPD01
RA/BTYP02
System External Cache Control Register Sxccr
L2PLL03
FLSHP02
PLL Value Size
CPU Control Register
Processor 0 External Cache Control Register P0XCCR
Processor 1 External Cache Control Register P1XCCR
CPU Control Register $FEF88300
W83C553 PIB Registers
Access Registers
ISA Local Resource Bus
Uart
NVRAM/RTC and Watchdog Timer Registers
General-Purpose Readable Jumpers
18. Module Configuration and Status Registers
Module Configuration and Status Registers
17. M48T59/559 Access Registers
PCI I/O Address Function
Cputype
CPU Configuration Register
Old CPU Configuration Register $FE000800
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
Pcixp PMC2P PMC1P Vmep Lanp
Base Module Feature Register
Base Module Feature Register Offset $0802
Base Module Status Register Offset $0803
Base Module Status Register Bmsr
Basetype
Basetype
Segment Display Register Offset $08C0
VME Registers
Seven-Segment Display Register
SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
SETSIG1
19. VME Registers
LM/SIG Control Register
SETSIG0
LM/SIG Status Register
Board Description and Memory Maps
Location Monitor Upper Base Address Register Offset $1002
Location Monitor Upper Base Address Register
Location Monitor Lower Base Address Register
Location Monitor Lower Base Address Register Offset $1003
SEM1
Semaphore Register
Semaphore Register 1 Offset $1004
Semaphore Register 2 Offset $1005
VME Geographical Address Register Vgar
Emulated Z8536 CIO Registers and Port Pins
20. Emulated Z8536 Access Registers
Emulated Z8536 Registers
21. Z8536 CIO Port Pin Assignments
Z8536 CIO Port Pins
Port Signal Direction Descriptions Pin Name
PC3 BASETYP1
ISA DMA Channels
PC2 BASETYP0
Page
Function Features
Features
Features of the Raven Asic
Block Diagram
Raven Block Diagram
MPC Bus Interface
MPC Address Mapping
MPC-to-PCI Address Decoding
MPC to PCI Address Translation
MPC Slave
Command Types MPC Slave Response
MPC Transfer Type Transaction Encoding
MPC Write Posting
MPC Master
MPC Transfer Type MPC Transfer Size TT0-TT4
PCI Command Code
MPC Transfer Types
MPC Bus Timer
MPC Arbiter
Configuration Registers
PCI Address Mapping
MPC Bus Address Space
PCI to MPC Address Decoding
RavenMPIC Control Registers
Decoder Priority
PCI Slave
Command Type Slave Response?
Command Types
Command Types PCI Slave Response
Addressing
Target-Initiated Termination
Exclusive Access
Device Selection
Fast Back-to-Back Transactions
PCI Write Posting
Parity
Cache Support
PCI Master
Entity Addressed
PCI Master Command Codes
PCI Command
Transfer Type
Combining, Merging, and Collapsing
Master Initiated Termination
Address/Data Stepping
Arbitration
Arbitration Latency
PCI Cycle Type
Generating PCI Cycles
Generating PCI Memory and I/O Cycles
Generating PCI Configuration Cycles
PCI Spread I/O Address Translation
Functional Description
Generating PCI Special Cycles
Device Number Address Bit
Generating PCI Interrupt Acknowledge Cycles
When MPC Devices are Big-Endian
Endian Conversion
Big- to Little-Endian Data Swap
Address Modification for Little-Endian Transfers
When MPC Devices are Little-Endian
Raven Registers and Endian Mode
Data Address Length Bytes Modification
Error Handling
SMA
Error Status Error Address Attributes
Transaction Ordering
Perr
Raven Registers
MPC Registers
Raven MPC Register Map
Devid
Vendor ID/Device ID Registers
Venid
Revid
General Control-Status/Feature Registers
Revision ID Register
Revision ID. Identifies the Raven revision level. This
Marb
Flbrd
Bhog
Mpic
Current MPC Data Bus Master
MIDx
Feat
Operation Reset $00 $B4
Prescaler Adjust Register
Operation Reset $00
MPC Arbiter Control Register
MPC Error Enable Register
Matom
Matoi
Smam
Rtam
Perri
Mato
MPC Error Status Register
OVF
PCI transaction. The bit may be cleared by writing it to a
Writing it to a 0 has no effect. When the Smam bit
SMA
RTA
Register
MPC Error Attribute Register Merat
Which originated the transfer in which the error occurred
TTx
Designates a selected byte
Piack
Operation Reset $0000
PCI Interrupt Acknowledge Register
Address $FEFF0030 Bit Name
END
Operation Reset $8000 $8080
Start
MPC Slave Address 3 Register
REN
MPC Slave Offset/Attribute 0,1 and 2 Registers
MSOFFx
WEN
MSOFF3
Wpen
IOM
Cycles. When clear, the corresponding MPC slave will
PCI Registers
$18 $7F
Raven PCI Configuration Register Map
$0C
$8C
$CF8
Operation Reset $4801 $1057
Raven PCI I/O Register Map
Offset $00 Bit Name
PCI Command/ Status Registers
Sigta
Dpar
Seltim
Rcvta
Base Register
Revision ID/ Class Code Registers
Class
Space
IO/MEM
RES
Ioba
PRE
Be compared with the upper 16 bits of the incoming PCI
To access MPC bus resources. The value of this field will
PCI Slave Address 0,1,2 and 3 Registers
Transfer type code which specifies the current transaction
PCI Slave Attribute/ Offset 0,1,2 and 3 Registers
INV
GBL
Conceptual perspective from the PCI bus
Configaddress Register
Perspective from the MPC bus in Big-Endian mode
FUN
Perspective from the MPC bus in Little-Endian mode
REG
DEV
BUS
EN Enable
Configdata Register
Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation Reset
Data ‘B’ Data ‘C’ Data ‘D’ Operation Reset
Architecture
Features
Raven Interrupt Controller
Processor’s Current Task Priority
Readability of CSR
Interrupt Source Priority
Interprocessor Interrupts IPI
Nesting of Interrupt Events
Spurious Vector Generation
Compatibility
Raven-Detected Errors
Timers
Interrupt Delivery Modes
Block Diagram Description
Raven Interrupt Controller
Interrupt Selector is
Program-Visible Registers
Interrupt Pending Register IPR
Interrupt Router
In-Service Register ISR
Interrupt Request Register IRR
Raven PCI Bridge Asic
10. RavenMPIC Register Map
Mpic Registers
RavenMPIC Registers
Off
$011E0
$010E0
$010F0
$100E0
$100F0
$101E0
$101F0
VID
Feature Reporting Register
Ncpu
Global Configuration Register
Offset $01020 Bit Name
STP
Processor 1. Writing a 1 to P1 will assert the Soft Reset
Vendor Identification Register
Processor Init Register
ACT
IPI Vector/Priority Registers
Mask
Prior
Vector fetch
Spurious Vector Register
Interrupt Acknowledge register is read during a spurious
Offset $010E0 Bit Name
Timer Current Count Registers
Timer Base Count Registers
Base Count. This field contains the 31-bit count for this
Count Inhibit. Setting this bit to 1 inhibits counting for
This timer. Setting the bit to 0 allows counting to proceed
Bit transitions from a 1 to a 0, the value is copied into
Timer Destination Registers
POL
Setting this bit to a 0 enables active low or negative edge
External Source Vector/Priority Registers
Sense
External Source Destination Registers
Raven-Detected Errors Vector/Priority Register
Offset $10200 Bit Name
Raven-Detected Errors Destination Register
Offset $10210 Bit Name
Offset Processor $20080 $21080 Bit Name
End-of-Interrupt Registers
Zero is assumed. Writing to this register signals the end
Interrupt Acknowledge Registers
End Of Interrupt. There is one EOI register per
External Interrupt Service
Programming Notes
Reset State
Dynamically Changing I/O Interrupt Configuration
Interprocessor Interrupts
Mode
EOI Register
Interrupt Acknowledge Register
Current Task Priority Level
Architectural Notes
Page
Features of the Falcon Chip Set
Dram
Block Diagrams
Falcon Pair Used with Dram in a System
Falcon Internal Data Paths Simplified
Overall Dram Connections
Four-beat Reads/Writes
Bit Ordering Convention
Performance
Single-beat Reads/Writes
Dram Speeds
2nd 3rd 4th
PowerPC 60x Bus to Dram Access Timing 70ns Page Devices
Clock Periods Required For Total Access Type
Beat
PowerPC 60x Bus to Dram Access Timing 60ns Page Devices
2nd 3rd 4th Clocks Beat
PowerPC Bus to Dram Access Timing 50ns Hyper Devices
ROM/Flash Speeds
Completing Data Transfers
PowerPC 60x Bus Interface
Responding to Address Transfers
Cache Coherency
Cycle Types
Cache Coherency Restrictions
L2 Cache Support
Error Reporting
Single-Bit
ROM/Flash Interface
Error Logging
Dram Tester
Functional Description
$XXFFFFFA $7FFFFE
$XXFFFFF8 $7FFFFC
$XXFFFFF9 $7FFFFD
$XXFFFFFB $7FFFFF
$X3FFFFF2 $7FFFFE
$X3FFFFF0 $7FFFFE
$X3FFFFF1 $7FFFFE
$X3FFFFF3 $7FFFFE
Refresh/Scrub
Blocks a and/or B Present, Blocks C and D Not Present
Blocks a and/or B Present, Blocks C and/or D Present
Chip Defaults
Dram Arbitration
CSR Architecture
CSR Accesses
External Register Set
Data Path for Reads from the Falcon Internal CSRs
Data Path for Writes to the Falcon Internal CSRs
Memory Map for Byte Reads to CSR
1906
Memory Map for 4-Byte Reads to CSR
Register Summary
Detailed Register Bit Descriptions
10. Register Summary
Programming Model
Test D3 Lower 32 Bits
Vendor/Device Register
Address $FEF80000 Bit Name
Revision ID/ General Control Register
Read Zero Read only
Ram spd0, ram spd1 Dram Speed Dram Type
Ram spd0,ram spd1
11. ram spd1,ram spd0 and Dram Type
Ram a/b/c/d siz0-2
Dram Attributes Register
Ram a/b/c/d en
0MB
BlockA/B/C/D Configurations
Ram a/b/c/d Block Size Devices Used Technology Comments
SIMM/DIMM
CLK Frequency Register
Dram Base Register
RAM A/B/C/D Base
CLK Frequency
Rwcb
ECC Control Register
Refdis
Read Zero
11707.00
Falcon ECC Memory Controller Chip Set
Mien
Tien
Sien
Mcken
Elog
Esen
Embt
Error Address Register
Address $FEF80038 Bit Name
Rtest0,rtest1,rtest2 Test Mode selected
13. rtest Encodings
Refresh/Scrub Address Register
Address $FEF80048 Bit Name
ROM a Base
1Mbyte of Block a also appears at $FFF00000
Rom a siz Block Size
14. ROM Block a Size Encoding
15. romarv and rombrv Encoding
1MB
16. Read/Write to ROM/Flash
Cycle Transfer Alignment Romx64 Romxwe Falcon Response
1Mbyte of Block B also appears at $FFF00000
ROM B Base/Size Register
ROM B Base
17. ROM Block B Size Encoding
Rom b siz Block Size
CTR32 is a 32-bit, free-running counter that increments
Dram Tester Control Registers
Bit Counter
Has been programmed properly. Notice that CTR32 is
Address $FEF80500 Bit Name
Power-Up Reset Status Register
Address $FEF80400 Bit Name
External Register Set
Address $FEF88000 $FEF8FFF8 Bit Name
Programming ROM/Flash Devices
Parity Checking on the PowerPC Bus
Software Considerations
Writing to the Control Registers
Sizing Dram
Software Considerations
1024MB 256MB 128MB 64MB 32MB 16MB
19. PowerPC 60x Address to Dram Address Mappings
18. Sizing Addresses
ROW
Bit Syndrome
20. Syndrome Codes Ordered by Bit in Error
ECC Codes
20. Syndrome Codes Ordered by Bit in Error
21. Single-Bit Errors Ordered by Syndrome Code
$AF $CF $EF
10. PowerPC Data to Dram Data Correspondence
Data Paths
22. PowerPC Data to Dram Data Mapping
Page
Universe VMEbus to PCI Chip
Features of the Universe Asic
− BLT, ADOH, RMW, Lock
Block Diagram
Architectural Diagram for the Universe
Universe as VMEbus Slave
PCI Bus Interface
Universe as VMEbus Master
Interrupter
Universe as PCI Slave Universe as PCI Master
DMA Controller
VMEbus Interrupt Handling
Universe Control and Status Registers Ucsr
Ucsr Access Mechanisms Universe Register Map
Offset Register Name
LSI2TO
LSI2BS
LSI2BD
LSI3BS
Dllue
Dcpp
Dgcs
Linten
VSI2CTL F2C
VSI0BD F0C
VSI1BS F1C
VSI2BS
Universe Chip Problems after PCI Reset
Description
Workarounds
Method
Example 1 MVME2600 Series Board Exhibits PCI Reset Problem
Examples
Example 2 MVME3600 Series Board Acts Differently
Run the init code and the LSI0 registers become
Example 3 Universe Chip is Checked at Tundra
Universe VMEbus to PCI Chip
Pci Bus Request PCI Masters
PCI Arbitration
PCI Arbitration Assignments
PIB
Interrupt Handling
MVME2300 Series Interrupt Architecture
Edge Polarity Interrupt Source
RavenMPIC
RavenMPIC Interrupt Assignments
Level
IRQ15
Interrupts
IRQ14
PIB Interrupt Handler Block Diagram
PIB PCI/ISA Interrupt Assignments
Edge
ISA DMA Channels
Exceptions
Sources of Reset
Reset switch
Sources of Reset
Soft Reset
Reset Sources and Devices Affected
Devices Affected
Cause Action
Error Notification and Handling
Error Notification and Handling
Endian Issues
Big-Endian Mode
Little-Endian Mode
PCI Domain
Processor/Memory Domain
Role of the Raven Asic
PCI/Ethernet
PCI-Graphics
Role of the Universe Asic
VMEbus Domain
ROM/Flash Initialization
ROM/Flash Bank Default
Default Mapping for FFF00000-FFFFFFFF
Page
Motorola Computer Group Documents
Document Title Publication Number
Manufacturers’ Documents
Document Title and Source Publication Number
MPCFPE/AD
EK-DE500-OM
IEC 821 BUS
Related Specifications
ANSI/IEEE
TIA/EIA-232
MPR-PPC-RPU-02
Isbn
Page
Glossary
O S S a R Y
Enhanced Integrated Drive Electronics. An improved version
PCI. Used in the reference platform specification. IBM
Computers developed by the IBM Corporation. PowerPC is
IBM
Signal Computing System Architecture. a hardware model for
See 10base-2
Page
Index
PCI 1-13 processor
IN-3
MPC
PCI
IN-5
Configaddress 2-56CONFIGDATA
IN-7
IN-8
