Texas Instruments TMS320 - page 15

NO.

WORDS

DESCRIPTION INSTRUCTION BIT CODE

MNEMONIC

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

NO.

WORDS

DESCRIPTION INSTRUCTION BIT CODE

MNEMONIC

D

D

D

D

D

D

D

PA

PA

TMS320C25

SPRS010B— MAY 1987— REVISED NOVEMBER 1990

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 15

Table 3. TMS320C25 Instruction Set Summary (continued)

BRANCH/CALL INSTRUCTIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BBranch unconditionally 2 1 1 1 1 1 1 1 1 1

BACC†Branch to address specified by accumulator 1 1100111000100101

BANZ Branch on auxiliary register not zero 2 111110111

BBNZ†Branch if TC bit ≠ 02111110011

BBZ†Branch if TC bit = 0 2 111110001

BC‡Branch on carry 2 010111101

BGEZ Branch if accumulator ≥ 02111101001

BGZ Branch if accumulator > 0 2 111100011

BIOZ Branch on I/O status = 0 2 111110101

BLEZ Branch if accumulator ≤ 02111100101

BLZ Branch if accumulator < 0 2 111100111

BNC‡Branch on no carry 2 010111111

BNV†Branch if no overflow 2 111101111

BNZ Branch if accumulator ≠ 02111101011

BV Branch on overflow 2 111100001

BZ Branch if accumulator = 0 2 111101101

CALA Call subroutine indirect 1 1100111000100100

CALL Call subroutine 2 111111101

RET Return from subroutine 1 1100111000100110

I/O AND DATA MEMORY OPERATIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BLKD†Block move from data memory to data memory 2 1 1 1 0 1 1 0 1 I

BLKP†Block move from program memory to data

memory 211111100I

DMOV Data move in data memory 1 01010110I

FORT†Format serial port registers 1 110011100000111FO

IN Input data from port 1 1000 I

OUT Output data to port 1 1110 I

RFSM‡Reset serial port frame synchronization mode 1 1100111000110110

RTXM†Reset serial port transmit mode 1 1100111000100000

RXF†Reset external flag 1 1100111000001100

SFSM‡Set serial port frame synchronization mode 1 1100111000110111

STXM†Set serial port transmit mode 1 1100111000100001

SXF†Set external flag 1 1100111000001101

TBLR Table read 1 01011000I

TBLW Table write 1 0 1 0 1 1 0 0 1 I

†These instructions are not included in the TMS320C1x instruction set.

‡These instructions are not included in the TMS32020 instruction set.

Contents

Main TMS320 SECOND-GENERATION DIGITAL SIGNAL PROCESSORS TMS320 SECOND-GENERATION PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS TMS320 SECOND-GENERATION DEVICES description introduction Page TMS320 SECOND-GENERATION DEVICES architecture SPRS010B MAY 1987 REVISED NOVEMBER 1990 functional block diagram (TMS320C2x) TMS320 SECOND-GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 Figure 1. Memory Maps 8 (a) Memory Maps After a CNFD Instruction (b) Memory Maps After a CNFP Instruction Program Program Data TMS320 SECOND-GENERATION DEVICES instruction set Page Table 3. TMS320C25 Instruction Set Summary Page Page Page Table 3. TMS320C25 Instruction Set Summary (concluded) Page development support TMS320 Family Development Support Reference Guide Table 4. TMS320 Second-Generation Software and Hardware Support TMS320 Family Development Support Reference Guide TMS320 SECOND-GENERATION documentation support specification overview Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies internal clock option mode, and parallel resonant, with an effective series resistance of 30 external clock option Figure 3. Test Load Circuit Figure 4. Voltage Reference Levels Page switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) Page Page internal clock option or overtone mode, and parallel resonant, with an effective series resistance of 30 Hardware Interfacing to the TMS320C25 external clock option Hardware Interfacing to the TMS320C25 (document number SPRA014A) for details on circuit operation. Figure 4. Test Load Circuit Figure 5. Voltage Reference Levels switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) TMS320C25, TMS320E25 EPROM PROGRAMMING electrical characteristics over specified temperature range (unless otherwise noted) recommended timing requirements for programming, TA = 25C, VCC = 6 V, VPP = 12.5 V (see Notes 14 and 15) Page Page Figure 7. External Clock Option Page switching characteristics over recommended operating conditions (see Notes 3 and 16) timing requirements over recommended operating conditions (see Notes 3 and 16) CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS Page TIMING DIAGRAMS clock timing memory read timing memory write timing one wait-state memory access timing reset timing interrupt timing (TMS32020) interrupt timing (TMS320C25) serial port receive timing serial port transmit timing BIO timing external flag timing BIO timing external flag timing HOLD timing (part A) HOLD timing (part B) HOLD timing (part A) HOLD timing (part B) TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25 TMS320C25FNL (PLCC) reflow soldering precautions no MECHANICAL DATA 68-pin GB grid array ceramic package (TMS32020, TMS320C25) 68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50) WARNING When reflow soldering is required, refer to page 54 for special handling instructions. MECHANICAL DATA 68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only) programming the TMS320E25 EPROM cell Pin Nomenclature (TMS320E25) Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout Page Figure 10. Fast Programming Flowchart Page Page Page Figure 13. EPROM Protect Timing Page Page PACKAGING INFORMATION PACKAGE OPTION ADDENDUM IMPORTANT NOTICE