Hold timing part B, CLKOUT1 CLKOUT2 | Texas Instruments TMS320

TMS32020

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

HOLD timing (part B)

CLKOUT1

CLKOUT2

ten(A-C1L)

STRB

td(C2H-H)²

HOLD

A15-A0

Valid

Valid

PS, DS, or IS

R/W

In

In

td(HH-AH)

D15-D0

HOLDA		N +	2	N + 3
N/A	N /A	N + 2		N + 3
FETCH
Dead	Dead	N + 1		N + 2

EXECUTE

ADVANCE INFORMATION

²HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.

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Image 51

Texas Instruments TMS320 specifications Hold timing part B, CLKOUT1 CLKOUT2, Holda Fetch

Contents

Description TMS320 SECOND-GENERATION Digital Signal Processors Signals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Wait States for Communication to Slower Off-Chip Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Memory Space Type ArchitectureTMS320 Second-Generation Device Overview Package SECOND-GENERATION Devices Functional block diagram TMS320C2x Memory control TimerScaling shifter 16 ⋅ 16-bit parallel multiplier Memory Maps TMS320 SECOND-GENERATION Devices Interrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary ZAC SUBT²XOR XORK² LTP ² ApacLPH ² LTA Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020 Development support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Documentation support Specification overview Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface Timing RS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock Option VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing IPP1 Eprom ProgrammingSee Notes 14 VPP INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock option Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high MIN TYP MAX Contrast Summary of Electrical SpecificationsClock characteristics and timing Parameter Serial port timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Hold timing Clock timing Timing Diagrams Memory read timing BR, PS, D SReady CLKOUT1 CLKOUT2 Strb Memory write timing MSC One wait-state memory access timing Iack Reset timing Interrupt timing TMS320C25 Interrupt timing TMS32020 Serial port transmit timing Serial port receive timing External flag timing BIO timing PC = N PC = N + Execute Hold timing part aHold Holda Hold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25 Mechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cell EPT VPP Pin Nomenclature TMS320E25VCC EPT Erasure TMS320E25 Programming Mode LevelsSignal Program Read Output Name ² PIN Verify Inhibit Disable Program verify Fast Programming Flowchart Output disable ReadROM protection and verification VSS Clkin EPT VPP TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VIH VIL PGM VPP VCC Rbit Eprom VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCC TMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging Information Important Notice