Hold timing part a, Holda, Execute | Texas Instruments TMS320

TMS32020

ADVANCE INFORMATION

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

HOLD timing (part A)

CLKOUT1
CLKOUT2
STRB
	td(C2H-H)²
HOLD
A15-A0	N	N + 1	N + 2
PS, DS,	Valid	Valid
or IS	Valid	Valid
or IS
R/W
			tdis(C1L-A)
D15-D0	In	In
			tdis(AL-A)

HOLDA

td(C1L-AL)

N	N +	1	N/A	N/A
FETCH
N ± 1	N		Dummy	Dead
EXECUTE

²HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.

50	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

Image 50

Texas Instruments TMS320 specifications Hold timing part a, Holda, Execute

Contents

TMS320 SECOND-GENERATION Digital Signal Processors Description Function PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Memory Space Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Wait States for Communication to Slower Off-Chip Package ArchitectureTMS320 Second-Generation Device Overview Type Functional block diagram TMS320C2x SECOND-GENERATION Devices 16 ⋅ 16-bit parallel multiplier TimerScaling shifter Memory control TMS320 SECOND-GENERATION Devices Memory Maps Multiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary XORK² SUBT²XOR ZAC LTA ApacLPH ² LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product Notification Development support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Specification overview Documentation support Parameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX Unit Hold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit External Clock Option Clkin VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing VPP Eprom ProgrammingSee Notes 14 IPP1 MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr Internal Clock Option External clock option CLKOUT1, CLKOUT2 Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Parameter Contrast Summary of Electrical SpecificationsClock characteristics and timing MIN TYP MAX Hold timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Serial port timing Timing Diagrams Clock timing Ready Memory read timingBR, PS, D S Memory write timing CLKOUT1 CLKOUT2 Strb One wait-state memory access timing MSC Reset timing Iack Interrupt timing TMS32020 Interrupt timing TMS320C25 Serial port receive timing Serial port transmit timing BIO timing External flag timing PC = N PC = N + Holda Hold timing part aHold Execute Holda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautions Parameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verification EPT Pin Nomenclature TMS320E25VCC EPT VPP Program Read Output Name ² PIN Verify Inhibit Disable TMS320E25 Programming Mode LevelsSignal Erasure Fast Programming Flowchart Program verify ROM protection and verification Output disableRead VIH VIL PGM VPP VCC TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VSS Clkin EPT VPP Eprom Rbit VIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS TMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25 Important Notice