Texas Instruments TMS320 - page 35

TMS320C25-50

SPRS010B— MAY 1987— REVISED NOVEMBER 1990

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 35

CLOCK CHARACTERISTICS AND TIMING

The TMS320C25-50 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2, CLKIN. The frequency of CLKOUT1

is one-fourth the crystal fundamental frequency. The crystal should be in either fundamental or overtone mode,

and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation of 1 mW, and be specified

at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned LC circuit.

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

fxInput clock frequency TA = 0°C to 70°C 6.7 51.2 MHz

fsx Serial port frequency TA = 0°C to 70°C 0 6.4 MHz

C1, C2 TA = 0°C to 70°C 10 pF

†The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to

fsx = 0 Hz.

X2/CLKIN

C2C1

X1

Crystal

Figure 6. Internal Clock Option

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLK, with X1 left

unconnected. The external frequency injected must conform to specifications listed in the following table.

switching characteristics over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

tc(C) CLKOUT1, CLKOUT2 cycle time 78.13 597 ns

td(CIH-C) CLKIN high to CLKOUT1, CLKOUT2, STRB high, low 12 27 ns

tf(C) CLKOUT1, CLKOUT2, STRB fall time 4 ns

tr(C) CLKOUT1, CLKOUT2, STRB rise time 4 ns

tw(CL) CLKOUT1, CLKOUT2, STRB low pulse duration 2Q – 7 2Q + 3 ns

tw(CH) CLKOUT1, CLKOUT2, STRB high pulse duration 2Q – 3 2Q + 7 ns

td(C1-C2) CLKOUT1 high to CLKOUT2 low,

CLKOUT2 high to CLKOUT1 high, etc. Q – 6 Q + 2 ns

NOTE 3: Q = 1/4 tc(C)

ADVANCE INFORMATION

Contents

Main TMS320 SECOND-GENERATION DIGITAL SIGNAL PROCESSORS TMS320 SECOND-GENERATION PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS TMS320 SECOND-GENERATION DEVICES description introduction Page TMS320 SECOND-GENERATION DEVICES architecture SPRS010B MAY 1987 REVISED NOVEMBER 1990 functional block diagram (TMS320C2x) TMS320 SECOND-GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 Figure 1. Memory Maps 8 (a) Memory Maps After a CNFD Instruction (b) Memory Maps After a CNFP Instruction Program Program Data TMS320 SECOND-GENERATION DEVICES instruction set Page Table 3. TMS320C25 Instruction Set Summary Page Page Page Table 3. TMS320C25 Instruction Set Summary (concluded) Page development support TMS320 Family Development Support Reference Guide Table 4. TMS320 Second-Generation Software and Hardware Support TMS320 Family Development Support Reference Guide TMS320 SECOND-GENERATION documentation support specification overview Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies internal clock option mode, and parallel resonant, with an effective series resistance of 30 external clock option Figure 3. Test Load Circuit Figure 4. Voltage Reference Levels Page switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) Page Page internal clock option or overtone mode, and parallel resonant, with an effective series resistance of 30 Hardware Interfacing to the TMS320C25 external clock option Hardware Interfacing to the TMS320C25 (document number SPRA014A) for details on circuit operation. Figure 4. Test Load Circuit Figure 5. Voltage Reference Levels switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) TMS320C25, TMS320E25 EPROM PROGRAMMING electrical characteristics over specified temperature range (unless otherwise noted) recommended timing requirements for programming, TA = 25C, VCC = 6 V, VPP = 12.5 V (see Notes 14 and 15) Page Page Figure 7. External Clock Option Page switching characteristics over recommended operating conditions (see Notes 3 and 16) timing requirements over recommended operating conditions (see Notes 3 and 16) CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS Page TIMING DIAGRAMS clock timing memory read timing memory write timing one wait-state memory access timing reset timing interrupt timing (TMS32020) interrupt timing (TMS320C25) serial port receive timing serial port transmit timing BIO timing external flag timing BIO timing external flag timing HOLD timing (part A) HOLD timing (part B) HOLD timing (part A) HOLD timing (part B) TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25 TMS320C25FNL (PLCC) reflow soldering precautions no MECHANICAL DATA 68-pin GB grid array ceramic package (TMS32020, TMS320C25) 68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50) WARNING When reflow soldering is required, refer to page 54 for special handling instructions. MECHANICAL DATA 68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only) programming the TMS320E25 EPROM cell Pin Nomenclature (TMS320E25) Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout Page Figure 10. Fast Programming Flowchart Page Page Page Figure 13. EPROM Protect Timing Page Page PACKAGING INFORMATION PACKAGE OPTION ADDENDUM IMPORTANT NOTICE