Or is D15-D0 TdHH-AH | Texas Instruments TMS320 specs

TMS320C25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

HOLD timing (part B)

CLKOUT1
CLKOUT2
	ten(A-C1L)
STRB
	td(C2H-H)²
HOLD
PS, DS,	Valid
or IS
R/W
D15-D0	In

td(HH-AH)

HOLDA

A15-A0		N + 2	N + 2
±	±	±	N + 2
FETCH
±	±	±	N + 1

EXECUTE

ADVANCE INFORMATION

²HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.

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Texas Instruments TMS320 specifications Or is D15-D0 TdHH-AH

Contents

Description TMS320 SECOND-GENERATION Digital Signal Processors Function PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-Chip TMS320 Second-Generation Device Overview ArchitecturePackage Type SECOND-GENERATION Devices Functional block diagram TMS320C2x Scaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory control Memory Maps TMS320 SECOND-GENERATION Devices Multiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZAC LPH ² ApacLTA LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020 Development support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Documentation support Specification overview Parameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface Timing Hold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock Option VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1 MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr CLKOUT1, CLKOUT2 Internal Clock Option External clock option Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAX RS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timing Clock timing Timing Diagrams Ready Memory read timingBR, PS, D S CLKOUT1 CLKOUT2 Strb Memory write timing MSC One wait-state memory access timing Iack Reset timing Interrupt timing TMS320C25 Interrupt timing TMS32020 Serial port transmit timing Serial port receive timing External flag timing BIO timing PC = N PC = N + Hold Hold timing part aHolda Execute Holda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25 Parameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cell VCC Pin Nomenclature TMS320E25EPT EPT VPP Signal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable Erasure Program verify Fast Programming Flowchart ROM protection and verification Output disableRead Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPP Rbit Eprom VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCC TMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging Information Important Notice