TMS32020
SPRS010B— MAY 1987— REVISED NOVEMBER 1990
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 23
timing requirements over recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
tc(C) CLKIN cycle time 195 597 ns
tf(CI) CLKIN fall time 10†ns
tr(CI) CLKIN rise time 10†ns
tw(CIL) CLKIN low pulse duration, tc(CI) = 50 ns (see Note 4) 40 ns
tw(CIH) CLKIN high pulse duration, tc(CI) = 50 ns (see Note 4) 40 ns
tsu(S) SYNC setup time before CLKIN low 10 Q – 10 ns
th(S) SYNC hold time from CLKIN low 15 ns
†Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
4. CLKIN duty cycle [tr(CI) + tw(CIH)]/t
c(CI) must be within 40-60%.
CL = 100 pF
2.15 V
RL = 825 Ω
Test
Point
From Output
Under Test
Figure 3. Test Load Circuit
0.80 V
0.92 V
1.88 V
2.0 V
0
VIH (Min)
VIL (Max)
(a) Input
0.6 V
0.8 V
2.2 V
2.4 V
0
VOH (Min)
VOL (Max)
(b) Output
Figure 4. Voltage Reference Levels
ADVANCE INFORMATION