Memory write timing | Texas Instruments TMS320 specs

TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

memory write timing

CLKOUT1

CLKOUT2

STRB

th(A)

tsu(A)

A15-A0,

BR, PS, DSValid or IS

R/W

READY
	tsu(D)W
	th(D)W
D15-D0	Data Out
ten(D)	tdis(D)

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Texas Instruments TMS320 specifications Memory write timing, CLKOUT1 CLKOUT2 Strb

Contents

Description TMS320 SECOND-GENERATION Digital Signal Processors PGA and PLCC/CER-QUAD PIN Assignments Signals DefinitionFunction PIN Introduction Wait States for Communication to Slower Off-Chip Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Memory Space Type ArchitectureTMS320 Second-Generation Device Overview Package SECOND-GENERATION Devices Functional block diagram TMS320C2x Memory control TimerScaling shifter 16 ⋅ 16-bit parallel multiplier Memory Maps TMS320 SECOND-GENERATION Devices External interface Interrupts and subroutinesMultiprocessing Instruction set Repeat featureAddressing modes Symbol Definition Instruction SymbolsInstruction set summary TMS320C25 Instruction Set Summary ZAC SUBT²XOR XORK² LTP ² ApacLPH ² LTA Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020 Development support Software Tools Part Number TMS320 Second-Generation Software and Hardware SupportHardware Tools Part Number Documentation support Specification overview MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP§ MAX Unit Internal clock option Clock Characteristics and TimingExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface Timing Hold Timing RS, INT, BIO, and XF TimingHold Holda Serial Port Timing MP/MC IOH INT Clkin / Clkx / ClkrTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock Option VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing IPP1 Eprom ProgrammingSee Notes 14 VPP CLKIN, CLKX, Clkr INT0 INT2 VIHMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock option Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high MIN TYP MAX Contrast Summary of Electrical SpecificationsClock characteristics and timing Parameter Serial port timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Hold timing Clock timing Timing Diagrams BR, PS, D S Memory read timingReady CLKOUT1 CLKOUT2 Strb Memory write timing MSC One wait-state memory access timing Iack Reset timing Interrupt timing TMS320C25 Interrupt timing TMS32020 Serial port transmit timing Serial port receive timing External flag timing BIO timing PC = N PC = N + Execute Hold timing part aHold Holda CLKOUT1 CLKOUT2 Hold timing part BHolda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25 Pin GB grid array ceramic package TMS32020, TMS320C25 Mechanical DataParameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cell EPT VPP Pin Nomenclature TMS320E25VCC EPT Erasure TMS320E25 Programming Mode LevelsSignal Program Read Output Name ² PIN Verify Inhibit Disable Program verify Fast Programming Flowchart Read Output disableROM protection and verification VSS Clkin EPT VPP TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VIH VIL PGM VPP VCC Rbit Eprom VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCC TMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging Information Important Notice