BIO timing, External flag timing | Texas Instruments TMS320 specs

TMS32020

ADVANCE INFORMATION

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

BIO timing

CLKOUT1

STRB

F	ETCH Branch Addres	s	F	ETCH Next Instructio	n

A15-A0	FETCH
A15-A0	BIOZ
	BIOZ
	PC = N	PC = N + 1	PC = N + 2	PC = N + 3

or Branch Address

tsu(IN)

th(IN)

BIO

Valid

external flag timing

CLKOUT1

	STRB
					td(XF)
	A15-A0	Valid	FETCH	Valid	Valid
	A15-A0	Valid	SXF/RXF	Valid	Valid
			SXF/RXF
		PC = N ± 1	PC = N	PC = N + 1	PC = N + 2
	XF				Valid

48	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

Image 48

Texas Instruments TMS320 specifications BIO timing, External flag timing

Contents

TMS320 SECOND-GENERATION Digital Signal Processors Description Signals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Key Features TMS32020 Bit-Reversed Indexed-Addressing Mode forMemory Space Wait States for Communication to Slower Off-Chip Architecture TMS320 Second-Generation Device OverviewPackage Type Functional block diagram TMS320C2x SECOND-GENERATION Devices Timer Scaling shifter16 ⋅ 16-bit parallel multiplier Memory control TMS320 SECOND-GENERATION Devices Memory Maps Interrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary SUBT² XORXORK² ZAC Apac LPH ²LTA LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product Notification Development support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Specification overview Documentation support Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX Unit RS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit External Clock Option Clkin VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing Eprom Programming See Notes 14VPP IPP1 INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL Internal Clock Option External clock option CLKOUT1, CLKOUT2 Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Contrast Summary of Electrical Specifications Clock characteristics and timingParameter MIN TYP MAX Memory and peripheral interface timing RS, INT, BIO, and XF timingHold timing Serial port timing Timing Diagrams Clock timing Memory read timing BR, PS, D SReady Memory write timing CLKOUT1 CLKOUT2 Strb One wait-state memory access timing MSC Reset timing Iack Interrupt timing TMS32020 Interrupt timing TMS320C25 Serial port receive timing Serial port transmit timing BIO timing External flag timing PC = N PC = N + Hold timing part a HoldHolda Execute Hold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautions Mechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verification Pin Nomenclature TMS320E25 VCCEPT EPT VPP TMS320E25 Programming Mode Levels SignalProgram Read Output Name ² PIN Verify Inhibit Disable Erasure Fast Programming Flowchart Program verify Output disable ReadROM protection and verification TMS320E25 Protect and Verify Eprom Mode Levels Eprom protectVIH VIL PGM VPP VCC VSS Clkin EPT VPP Eprom Rbit VIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS TMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25 Important Notice