Interrupt timing TMS32020 | Texas Instruments instruction

ADVANCE INFORMATION

TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

interrupt timing (TMS32020)

CLKOUT1
STRB
	tsu(IN)		th(IN)
	tw(IN)
INT2-INT0
	tf(IN)		td(IACK)
A15-A0	FETCH N	FETCH N + 1	FETCH I	FETCH I + 1
	td(IACK)
IACK

interrupt timing (TMS320C25)

CLKOUT1
	tsu(IN)
STRB
		th(IN)
	tw(IN)
INT2-INT0
	tf(IN)	td(IACK)
A15-A0	FETCH N	FETCH N + 1	FETCH N + 2	N + 3	FETCH I
	td(IACK)
IACK

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Image 46

Texas Instruments specifications Interrupt timing TMS32020, Interrupt timing TMS320C25

Contents

TMS320 SECOND-GENERATION Digital Signal Processors Description PGA and PLCC/CER-QUAD PIN Assignments Signals DefinitionFunction PIN Introduction Memory Space Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Wait States for Communication to Slower Off-Chip Package ArchitectureTMS320 Second-Generation Device Overview Type Functional block diagram TMS320C2x SECOND-GENERATION Devices 16 ⋅ 16-bit parallel multiplier TimerScaling shifter Memory control TMS320 SECOND-GENERATION Devices Memory Maps External interface Interrupts and subroutinesMultiprocessing Instruction set Repeat featureAddressing modes Symbol Definition Instruction SymbolsInstruction set summary TMS320C25 Instruction Set Summary XORK² SUBT²XOR ZAC LTA ApacLPH ² LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product Notification Development support Software Tools Part Number TMS320 Second-Generation Software and Hardware SupportHardware Tools Part Number Specification overview Documentation support MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP§ MAX Unit Internal clock option Clock Characteristics and TimingExternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX Unit Hold Timing RS, INT, BIO, and XF TimingHold Holda Serial Port Timing MP/MC IOH INT Clkin / Clkx / ClkrTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit External Clock Option Clkin VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing VPP Eprom ProgrammingSee Notes 14 IPP1 CLKIN, CLKX, Clkr INT0 INT2 VIHMP/MC VIL Internal Clock Option External clock option CLKOUT1, CLKOUT2 Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Parameter Contrast Summary of Electrical SpecificationsClock characteristics and timing MIN TYP MAX Hold timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Serial port timing Timing Diagrams Clock timing BR, PS, D S Memory read timingReady Memory write timing CLKOUT1 CLKOUT2 Strb One wait-state memory access timing MSC Reset timing Iack Interrupt timing TMS32020 Interrupt timing TMS320C25 Serial port receive timing Serial port transmit timing BIO timing External flag timing PC = N PC = N + Holda Hold timing part aHold Execute CLKOUT1 CLKOUT2 Hold timing part BHolda Fetch Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautions Pin GB grid array ceramic package TMS32020, TMS320C25 Mechanical DataParameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verification EPT Pin Nomenclature TMS320E25VCC EPT VPP Program Read Output Name ² PIN Verify Inhibit Disable TMS320E25 Programming Mode LevelsSignal Erasure Fast Programming Flowchart Program verify Read Output disableROM protection and verification VIH VIL PGM VPP VCC TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VSS Clkin EPT VPP Eprom Rbit VIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS TMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25 Important Notice