Fetch Execute | Texas Instruments TMS320 specification

TMS320C25

ADVANCE INFORMATION

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

HOLD timing (part A)

CLKOUT1
CLKOUT2
STRB
	td(C2H-H)²
HOLD
A15-A0	N	N + 1	N + 2
PS, DS,	Valid	Valid
or IS	Valid	Valid
or IS
R/W
			tdis(C1L-A)
D15-D0	In	In
			tdis(AL-A)

HOLDA

td(C1L-AL)

N	N + 1	±	±
FETCH
N ± 2	N ± 1	N	±
EXECUTE

²HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.

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Image 52

Texas Instruments TMS320 specifications Fetch Execute

Contents

TMS320 SECOND-GENERATION Digital Signal Processors Description PGA and PLCC/CER-QUAD PIN Assignments Signals DefinitionFunction PIN Introduction Key Features TMS32020 Bit-Reversed Indexed-Addressing Mode forMemory Space Wait States for Communication to Slower Off-Chip Architecture TMS320 Second-Generation Device OverviewPackage Type Functional block diagram TMS320C2x SECOND-GENERATION Devices Timer Scaling shifter16 ⋅ 16-bit parallel multiplier Memory control TMS320 SECOND-GENERATION Devices Memory Maps External interface Interrupts and subroutinesMultiprocessing Instruction set Repeat featureAddressing modes Symbol Definition Instruction SymbolsInstruction set summary TMS320C25 Instruction Set Summary SUBT² XORXORK² ZAC Apac LPH ²LTA LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product Notification Development support Software Tools Part Number TMS320 Second-Generation Software and Hardware SupportHardware Tools Part Number Specification overview Documentation support MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP§ MAX Unit Internal clock option Clock Characteristics and TimingExternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX Unit Hold Timing RS, INT, BIO, and XF TimingHold Holda Serial Port Timing MP/MC IOH INT Clkin / Clkx / ClkrTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit External Clock Option Clkin VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing Eprom Programming See Notes 14VPP IPP1 CLKIN, CLKX, Clkr INT0 INT2 VIHMP/MC VIL Internal Clock Option External clock option CLKOUT1, CLKOUT2 Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Contrast Summary of Electrical Specifications Clock characteristics and timingParameter MIN TYP MAX Memory and peripheral interface timing RS, INT, BIO, and XF timingHold timing Serial port timing Timing Diagrams Clock timing BR, PS, D S Memory read timingReady Memory write timing CLKOUT1 CLKOUT2 Strb One wait-state memory access timing MSC Reset timing Iack Interrupt timing TMS32020 Interrupt timing TMS320C25 Serial port receive timing Serial port transmit timing BIO timing External flag timing PC = N PC = N + Hold timing part a HoldHolda Execute CLKOUT1 CLKOUT2 Hold timing part BHolda Fetch Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautions Pin GB grid array ceramic package TMS32020, TMS320C25 Mechanical DataParameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verification Pin Nomenclature TMS320E25 VCCEPT EPT VPP TMS320E25 Programming Mode Levels SignalProgram Read Output Name ² PIN Verify Inhibit Disable Erasure Fast Programming Flowchart Program verify Read Output disableROM protection and verification TMS320E25 Protect and Verify Eprom Mode Levels Eprom protectVIH VIL PGM VPP VCC VSS Clkin EPT VPP Eprom Rbit VIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS TMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25 Important Notice