Texas Instruments TMS320 Table 3. TMS320C25 Instruction Set Summary

S

NO.

WORDS

D

DESCRIPTION

D

D

K

D

D

S

D

S

SD

D

S

D

S

S

X D

DX

S D

D

D

D

K

D

MNEMONIC

K

INSTRUCTION BIT CODE

TMS320C25

SPRS010B— MAY 1987— REVISED NOVEMBER 1990

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001

12

Table 3. TMS320C25 Instruction Set Summary

ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ABS Absolute value of accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 1

ADD Add to accumulator with shift 1 0000 I

ADDC‡Add to accumulator with carry 1 01000011I

ADDH Add to high accumulator 1 01001000I

ADDK‡Add to accumulator short immediate 1 11001100

ADDS Add to low accumulator with sign

extension suppressed 101001001I

ADDT Add to accumulator with shift specified by

T register 101001010I

ADLK†Add to accumulator long immediate with shift 2 11 0 1 00000010

AND AND with accumulator 1 01001110I

ANDK†AND immediate with accumulator with shift 2 11 0 1 00000100

CMPL†Complement accumulator 1 1100111000100111

LAC Load accumulator with shift 1 0010 I

LACK Load accumulator immediate short 1 11001010

LACT†Load accumulator with shift specified by

T register 101000010I

LALK†Load accumulator long immediate with shift 2 110 1 00000 001

NEG†Negate accumulator 1 1100111000100011

NORM†Normalize contents of accumulator 1 110011101XXX0010

OR OR with accumulator 1 01001101I

ORK†OR immediate with accumulator with shift 2 11 0 1 00000101

ROL‡Rotate accumulator left 1 1100111000110100

ROR‡Rotate accumulator right 1 1100111000110101

SACH Store high accumulator with shift 1 01101 I

SACL Store low-order accumulator with shift 1 01100 I

SBLK† Subtract from accumulator long immediate

with shift 211 0 1 00000011

SFL†Shift accumulator left 1 1100111000011000

SFR†Shift accumulator right 1 1100111000011001

SUB Subtract from accumulator with shift 1 0001 I

SUBB‡Subtract from accumulator with borrow 1 01001111I

SUBC Conditional subtract 1 01000111I

SUBH Subtract from high accumulator 1 01000100I

SUBK‡Subtract from accumulator short immediate 1 11001101

SUBS Subtract from low accumulator with sign

extension suppressed 1 0 1 0 0 0 1 0 1 I

†These instructions are not included in the TMS320C1x instruction set.

‡These instructions are not included in the TMS32020 instruction set.

Contents

Main TMS320 SECOND-GENERATION DIGITAL SIGNAL PROCESSORS TMS320 SECOND-GENERATION PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS TMS320 SECOND-GENERATION DEVICES description introduction Page TMS320 SECOND-GENERATION DEVICES architecture SPRS010B MAY 1987 REVISED NOVEMBER 1990 functional block diagram (TMS320C2x) TMS320 SECOND-GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 Figure 1. Memory Maps 8 (a) Memory Maps After a CNFD Instruction (b) Memory Maps After a CNFP Instruction Program Program Data TMS320 SECOND-GENERATION DEVICES instruction set Page Table 3. TMS320C25 Instruction Set Summary Page Page Page Table 3. TMS320C25 Instruction Set Summary (concluded) Page development support TMS320 Family Development Support Reference Guide Table 4. TMS320 Second-Generation Software and Hardware Support TMS320 Family Development Support Reference Guide TMS320 SECOND-GENERATION documentation support specification overview Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies internal clock option mode, and parallel resonant, with an effective series resistance of 30 external clock option Figure 3. Test Load Circuit Figure 4. Voltage Reference Levels Page switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) Page Page internal clock option or overtone mode, and parallel resonant, with an effective series resistance of 30 Hardware Interfacing to the TMS320C25 external clock option Hardware Interfacing to the TMS320C25 (document number SPRA014A) for details on circuit operation. Figure 4. Test Load Circuit Figure 5. Voltage Reference Levels switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) TMS320C25, TMS320E25 EPROM PROGRAMMING electrical characteristics over specified temperature range (unless otherwise noted) recommended timing requirements for programming, TA = 25C, VCC = 6 V, VPP = 12.5 V (see Notes 14 and 15) Page Page Figure 7. External Clock Option Page switching characteristics over recommended operating conditions (see Notes 3 and 16) timing requirements over recommended operating conditions (see Notes 3 and 16) CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS Page TIMING DIAGRAMS clock timing memory read timing memory write timing one wait-state memory access timing reset timing interrupt timing (TMS32020) interrupt timing (TMS320C25) serial port receive timing serial port transmit timing BIO timing external flag timing BIO timing external flag timing HOLD timing (part A) HOLD timing (part B) HOLD timing (part A) HOLD timing (part B) TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25 TMS320C25FNL (PLCC) reflow soldering precautions no MECHANICAL DATA 68-pin GB grid array ceramic package (TMS32020, TMS320C25) 68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50) WARNING When reflow soldering is required, refer to page 54 for special handling instructions. MECHANICAL DATA 68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only) programming the TMS320E25 EPROM cell Pin Nomenclature (TMS320E25) Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout Page Figure 10. Fast Programming Flowchart Page Page Page Figure 13. EPROM Protect Timing Page Page PACKAGING INFORMATION PACKAGE OPTION ADDENDUM IMPORTANT NOTICE