TMS320C25 Instruction Set Summary | Texas Instruments specification

12

TMS320C25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

Table 3. TMS320C25 Instruction Set Summary

ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS

MNEMONIC	DESCRIPTION	NO.					INSTRUCTION BIT CODE
MNEMONIC	DESCRIPTION	WORDS

			15	14	13	12	11		10			9	8		7	6		5	4		3			2	1	0
			15	14	13	12	11		10			9	8		7	6		5	4		3			2	1	0

ABS	Absolute value of accumulator	1	1	1	0	0	1		1			1	0		0	0		0	1		1			0	1	1
ADD	Add to accumulator with shift	1	0	0	0	0					S				I								D
ADD	Add to accumulator with shift	1	0	0	0	0					S				I								D
ADDC³	Add to accumulator with carry	1	0	1	0	0	0		0			1	1		I								D
ADDC³	Add to accumulator with carry	1	0	1	0	0	0		0			1	1		I								D
ADDH	Add to high accumulator	1	0	1	0	0	1		0			0	0		I								D
ADDH	Add to high accumulator	1	0	1	0	0	1		0			0	0		I								D
ADDK³	Add to accumulator short immediate	1	1	1	0	0	1		1			0	0								K
ADDK³	Add to accumulator short immediate	1	1	1	0	0	1		1			0	0								K
ADDS	Add to low accumulator with sign	1	0	1	0	0	1		0			0	1		I								D
ADDS	extension suppressed	1	0	1	0	0	1		0			0	1		I								D
	extension suppressed
ADDT	Add to accumulator with shift specified by	1	0	1	0	0	1		0			1	0		I								D
ADDT	T register	1	0	1	0	0	1		0			1	0		I								D
	T register
ADLK²	Add to accumulator long immediate with shift	2	1	1	0	1					S				0	0		0	0		0			0	1	0
ADLK²	Add to accumulator long immediate with shift	2	1	1	0	1					S				0	0		0	0		0			0	1	0
AND	AND with accumulator	1	0	1	0	0	1		1			1	0		I								D
AND	AND with accumulator	1	0	1	0	0	1		1			1	0		I								D
ANDK²	AND immediate with accumulator with shift	2	1	1	0	1					S				0	0		0	0		0			1	0	0
ANDK²	AND immediate with accumulator with shift	2	1	1	0	1					S				0	0		0	0		0			1	0	0
CMPL²	Complement accumulator	1	1	1	0	0	1		1			1	0		0	0		1	0		0			1	1	1
LAC	Load accumulator with shift	1	0	0	1	0					S				I								D


LACK	Load accumulator immediate short	1	1	1	0	0	1		0			1	0								K
LACK	Load accumulator immediate short	1	1	1	0	0	1		0			1	0								K
LACT²	Load accumulator with shift specified by	1	0	1	0	0	0		0			1	0		I								D
LACT²	T register	1	0	1	0	0	0		0			1	0		I								D
	T register
LALK²	Load accumulator long immediate with shift	2	1	1	0	1					S				0	0		0	0		0			0	0	1
LALK²	Load accumulator long immediate with shift	2	1	1	0	1					S				0	0		0	0		0			0	0	1
NEG²	Negate accumulator	1	1	1	0	0	1		1			1	0		0	0		1	0		0			0	1	1
NORM²	Normalize contents of accumulator	1	1	1	0	0	1		1			1	0		1	X		X	X		0			0	1	0
OR	OR with accumulator	1	0	1	0	0	1		1			0	1		I								D
OR	OR with accumulator	1	0	1	0	0	1		1			0	1		I								D
ORK²	OR immediate with accumulator with shift	2	1	1	0	1					S				0	0		0	0		0			1	0	1
ORK²	OR immediate with accumulator with shift	2	1	1	0	1					S				0	0		0	0		0			1	0	1
ROL³	Rotate accumulator left	1	1	1	0	0	1		1			1	0		0	0		1	1		0			1	0	0
ROR³	Rotate accumulator right	1	1	1	0	0	1		1			1	0		0	0		1	1		0			1	0	1
SACH	Store high accumulator with shift	1	0	1	1	0	1					X			I								D
SACH	Store high accumulator with shift	1	0	1	1	0	1					X			I								D
SACL	Store low-order accumulator with shift	1	0	1	1	0	0					X			I								D
SACL	Store low-order accumulator with shift	1	0	1	1	0	0					X			I								D
SBLK²	Subtract from accumulator long immediate	2	1	1	0	1					S				0	0		0	0		0			0	1	1
	with shift



SFL²	Shift accumulator left	1	1	1	0	0	1		1			1	0		0	0		0	1		1			0	0	0
SFR²	Shift accumulator right	1	1	1	0	0	1		1			1	0		0	0		0	1		1			0	0	1
SUB	Subtract from accumulator with shift	1	0	0	0	1					S				I								D
SUB	Subtract from accumulator with shift	1	0	0	0	1					S				I								D
SUBB³	Subtract from accumulator with borrow	1	0	1	0	0	1		1			1	1		I								D
SUBB³	Subtract from accumulator with borrow	1	0	1	0	0	1		1			1	1		I								D
SUBC	Conditional subtract	1	0	1	0	0	0		1			1	1		I								D
SUBC	Conditional subtract	1	0	1	0	0	0		1			1	1		I								D
SUBH	Subtract from high accumulator	1	0	1	0	0	0		1			0	0		I								D
SUBH	Subtract from high accumulator	1	0	1	0	0	0		1			0	0		I								D
SUBK³	Subtract from accumulator short immediate	1	1	1	0	0	1		1			0	1								K
SUBK³	Subtract from accumulator short immediate	1	1	1	0	0	1		1			0	1								K
SUBS	Subtract from low accumulator with sign	1	0	1	0	0	0		1			0	1		I								D
SUBS	extension suppressed	1	0	1	0	0	0		1			0	1		I								D
	extension suppressed

² These instructions are not included in the TMS320C1x instruction set.
³ These instructions are not included in the TMS32020 instruction set.

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Image 12

Texas Instruments specifications TMS320C25 Instruction Set Summary

Contents

TMS320 SECOND-GENERATION Digital Signal Processors Description Signals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Key Features TMS32020 Bit-Reversed Indexed-Addressing Mode forMemory Space Wait States for Communication to Slower Off-Chip Architecture TMS320 Second-Generation Device OverviewPackage Type Functional block diagram TMS320C2x SECOND-GENERATION Devices Timer Scaling shifter16 ⋅ 16-bit parallel multiplier Memory control TMS320 SECOND-GENERATION Devices Memory Maps Interrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary SUBT² XORXORK² ZAC Apac LPH ²LTA LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product Notification Development support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Specification overview Documentation support Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX Unit RS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit External Clock Option Clkin VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing Eprom Programming See Notes 14VPP IPP1 INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL Internal Clock Option External clock option CLKOUT1, CLKOUT2 Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Contrast Summary of Electrical Specifications Clock characteristics and timingParameter MIN TYP MAX Memory and peripheral interface timing RS, INT, BIO, and XF timingHold timing Serial port timing Timing Diagrams Clock timing Memory read timing BR, PS, D SReady Memory write timing CLKOUT1 CLKOUT2 Strb One wait-state memory access timing MSC Reset timing Iack Interrupt timing TMS32020 Interrupt timing TMS320C25 Serial port receive timing Serial port transmit timing BIO timing External flag timing PC = N PC = N + Hold timing part a HoldHolda Execute Hold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautions Mechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verification Pin Nomenclature TMS320E25 VCCEPT EPT VPP TMS320E25 Programming Mode Levels SignalProgram Read Output Name ² PIN Verify Inhibit Disable Erasure Fast Programming Flowchart Program verify Output disable ReadROM protection and verification TMS320E25 Protect and Verify Eprom Mode Levels Eprom protectVIH VIL PGM VPP VCC VSS Clkin EPT VPP Eprom Rbit VIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS TMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25 Important Notice