RS, INT, BIO, and XF Timing, Hold Timing | Texas Instruments TMS320

TMS32020

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

RS, INT, BIO, AND XF TIMING

switching characteristics over recommended operating conditions (see Note 3 and 8)

			PARAMETER			MIN	TYP	MAX	UNIT

td(RS)	CLKOUT1 low to reset state entered							45	ns
td(IACK)	CLKOUT1 to		valid			± 25	0	25	ns
td(IACK)	CLKOUT1 to	IACK	valid			± 25	0	25	ns
td(XF)	XF valid before falling edge of					Q ± 30			ns
td(XF)	XF valid before falling edge of			STRB		Q ± 30			ns

NOTES: 3. Q = 1/4tc(C).

8.RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur.

timing requirements over recommended operating conditions (see Note 3 and 8)

									MIN	NOM MAX	UNIT

tsu(IN)									50		ns
tsu(IN)		INT/BIO/RS setup before CLKOUT1 high							50		ns
th(IN)									0		ns
th(IN)	INT/BIO/RS hold after CLKOUT1 high								0		ns
t										15²	ns
t	INT/BIO fall time									15²	ns
f(IN)
tw(IN)									tc(C)		ns
tw(IN)		INT/BIO low pulse duration							tc(C)		ns
tw(RS)			low pulse duration						3tc(C)		ns
tw(RS)	RS		low pulse duration						3tc(C)		ns

²Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C).

8.RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur.

HOLD TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER

MIN

TYP MAX

UNIT

t

low after CLKOUT1 low

±25²

25

ns

HOLDA

d(C1L-AL)

tdis(AL-A)

low to address three-state

15²

ns

HOLDA

tdis(C1L-A)

Address three-state after CLKOUT1 low

mode, see Note 9)

30²

ns

(HOLD

td(HH-AH)

high to

high

50

ns

HOLD

HOLDA

ten(A-C1L)

Address driven before CLKOUT1 low

mode, see Note 9)

10²

ns

(HOLD

²Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C).

9.A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as ªaddress.º

timing requirements over recommended operating conditions (see Note 3)

			MIN NOM	MAX	UNIT

td(C2H-H)		valid after CLKOUT2 high		Q ± 45	ns
td(C2H-H)	HOLD	valid after CLKOUT2 high		Q ± 45	ns

NOTE 3: Q = 1/4tc(C).

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25

Image 25

Texas Instruments TMS320 specifications RS, INT, BIO, and XF Timing, Hold Timing, Hold Holda

Contents

Description TMS320 SECOND-GENERATION Digital Signal Processors PGA and PLCC/CER-QUAD PIN Assignments Signals DefinitionFunction PIN Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-Chip TMS320 Second-Generation Device Overview ArchitecturePackage Type SECOND-GENERATION Devices Functional block diagram TMS320C2x Scaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory control Memory Maps TMS320 SECOND-GENERATION Devices External interface Interrupts and subroutinesMultiprocessing Instruction set Repeat featureAddressing modes Symbol Definition Instruction SymbolsInstruction set summary TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZAC LPH ² ApacLTA LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020 Development support Software Tools Part Number TMS320 Second-Generation Software and Hardware SupportHardware Tools Part Number Documentation support Specification overview MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP§ MAX Unit Internal clock option Clock Characteristics and TimingExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface Timing Hold Timing RS, INT, BIO, and XF TimingHold Holda Serial Port Timing MP/MC IOH INT Clkin / Clkx / ClkrTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock Option VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1 CLKIN, CLKX, Clkr INT0 INT2 VIHMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock option Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAX RS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timing Clock timing Timing Diagrams BR, PS, D S Memory read timingReady CLKOUT1 CLKOUT2 Strb Memory write timing MSC One wait-state memory access timing Iack Reset timing Interrupt timing TMS320C25 Interrupt timing TMS32020 Serial port transmit timing Serial port receive timing External flag timing BIO timing PC = N PC = N + Hold Hold timing part aHolda Execute CLKOUT1 CLKOUT2 Hold timing part BHolda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25 Pin GB grid array ceramic package TMS32020, TMS320C25 Mechanical DataParameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cell VCC Pin Nomenclature TMS320E25EPT EPT VPP Signal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable Erasure Program verify Fast Programming Flowchart Read Output disableROM protection and verification Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPP Rbit Eprom VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCC TMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging Information Important Notice