Reset timing, Iack | Texas Instruments TMS320 manual

TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

reset timing

CLKOUT1
tsu(IN)	td(RS)	tsu(IN)
		th(IN)
RS
	tw(RS)
A15-A0			Valid
			Fetch
			Location 0
D15-D0
		Valid	Begin
			Begin
			Program
PS			Execution

STRB

Control

Signals²

IACK

Serial Port

Control³

²Control signals are DS, IS, R/W, and XF. ³ Serial port controls are DX and FSX.

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45

Image 45

Texas Instruments TMS320 specifications Reset timing, Iack

Contents

Description TMS320 SECOND-GENERATION Digital Signal Processors Signals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-Chip TMS320 Second-Generation Device Overview ArchitecturePackage Type SECOND-GENERATION Devices Functional block diagram TMS320C2x Scaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory control Memory Maps TMS320 SECOND-GENERATION Devices Interrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZAC LPH ² ApacLTA LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020 Development support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Documentation support Specification overview Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface Timing RS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock Option VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1 INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock option Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAX RS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timing Clock timing Timing Diagrams Memory read timing BR, PS, D SReady CLKOUT1 CLKOUT2 Strb Memory write timing MSC One wait-state memory access timing Iack Reset timing Interrupt timing TMS320C25 Interrupt timing TMS32020 Serial port transmit timing Serial port receive timing External flag timing BIO timing PC = N PC = N + Hold Hold timing part aHolda Execute Hold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25 Mechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cell VCC Pin Nomenclature TMS320E25EPT EPT VPP Signal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable Erasure Program verify Fast Programming Flowchart Output disable ReadROM protection and verification Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPP Rbit Eprom VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCC TMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging Information Important Notice