TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

K1/26

 

A12

K8/40

D2

E1/16

 

D14

A5/3

 

 

 

 

 

 

 

 

 

 

 

 

 

H1/22

VCC

H2/23

 

 

 

INT2

 

 

 

 

 

A1

K2/28

 

A13

L9/41

D3

D2/15

 

D15

B6/2

 

 

 

 

 

 

 

 

 

 

 

 

 

J11/46

VCC

L6/35

 

 

 

IS

 

 

 

 

 

 

 

 

 

 

A2

L3/29

 

A14

K9/42

D4

D1/14

 

DR

J1/24

 

 

 

 

 

 

 

 

 

 

 

 

²

A6/1

VSS

B1/10

 

 

 

MP/MC

A3

K3/30

 

A15

L10/43

D5

C2/13

 

 

 

 

 

 

 

K10/45

 

 

 

 

 

 

 

 

 

 

 

 

 

C10/59

VSS

K11/44

 

 

DS

 

 

 

 

 

 

MSC

 

 

 

A4

L4/31

 

 

 

 

B7/68

D6

C1/12

 

DX

E11/54

 

 

 

 

 

 

 

 

 

 

 

 

 

J10/47

VSS

L2/27

 

BIO

 

 

 

PS

 

 

 

 

 

A5

K4/32

 

 

 

 

G11/50

D7

B2/11

 

FSR

J2/25

 

READY

B8/66

XF

D11/56

 

BR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

L5/33

 

CLKOUT1

C11/58

D8

A2/9

 

FSX

F10/53

 

 

 

 

 

 

 

 

 

 

 

 

 

A8/65

X1

G10/51

 

 

 

RS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

K5/34

 

CLKOUT2

D10/57

D9

B3/8

 

 

 

 

 

 

 

A7/67

 

 

 

 

 

 

 

 

 

 

 

 

 

H11/48

X2/CLKIN

F11/52

 

 

HOLD

 

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A8

K6/36

 

CLKR

B9/64

D10

A3/7

 

 

 

 

 

 

 

E10/55

 

 

 

 

 

 

 

 

 

 

 

 

 

H10/49

 

 

 

 

HOLDA

 

 

STRB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A9

L7/37

 

CLKX

A9/63

D11

B4/6

 

 

 

 

 

 

 

B11/60

 

 

 

 

 

 

 

 

 

 

 

 

 

F2/19

 

 

 

 

IACK

 

 

SYNC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A10

K7/38

 

D0

F1/18

D12

A4/5

 

 

 

 

 

 

 

G1/20

 

VCC

A10/61

 

 

 

 

INT0

 

 

 

 

A11

L8/39

 

D1

E2/17

D13

B5/4

 

 

 

 

 

 

 

G2/21

 

VCC

B10/62

 

 

 

 

INT1

 

 

 

 

²On the TMS32020, MP/MC must be connected to VCC.

 

 

SIGNALS

I/O/Z³

DEFINITION

 

VCC

I

5-V supply pins

 

VSS

I

Ground pins

 

X1

O

Output from internal oscillator for crystal

 

X2/CLKIN

I

Input to internal oscillator from crystal or external clock

 

CLKOUT1

O

Master clock output (crystal or CLKIN frequency/4)

 

CLKOUT2

O

A second clock output signal

 

D15-D0

I/O/Z

16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/O spaces.

 

A15-A0

O/Z

16-bit address bus A15 (MSB) through A0 (LSB)

 

PS,

 

 

 

 

DS,

 

 

 

IS

 

O/Z

Program, data, and I/O space select signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O/Z

Read/write signal

 

R/W

 

STRB

 

 

 

 

 

O/Z

Strobe signal

 

RS

 

 

 

 

 

 

 

 

 

 

I

Reset input

 

INT2

-

INT0

 

I

External user interrupt inputs

 

 

 

 

 

 

 

 

 

I

Microprocessor/microcomputer mode select pin

 

MP/MC

 

MSC

 

 

 

 

O

Microstate complete signal

 

IACK

 

 

 

O

Interrupt acknowledge signal

 

READY

I

Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is complete.

 

BR

 

 

 

 

O

Bus request signal. Asserted when the TMS320C2x requires access to an external global data memory space.

 

XF

O

External flag output (latched software-programmable signal)

 

HOLD

 

 

I

Hold input. When asserted, TMS320C2x goes into an idle mode and places the data, address, and control lines in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the high impedance state.

 

HOLDA

 

O

Hold acknowledge signal

 

SYNC

 

I

Synchronization input

 

BIO

 

I

Branch control input. Polled by BIOZ instruction.

 

DR

I

Serial data receive input

 

CLKR

I

Clock for receive input for serial port

 

FSR

I

Frame synchronization pulse for receive input

 

DX

O/Z

Serial data transmit output

 

CLKX

I

Clock for transmit output for serial port

 

FSX

I/O/Z

Frame synchronization pulse for transmit. Configuration as either an input or an output.

³ I/O/Z denotes input/output/high-impedance state.

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Texas Instruments TMS320 specifications PGA and PLCC/CER-QUAD PIN Assignments, Function PIN, Signals Definition