Texas Instruments TMS320 - page 24

TMS32020

SPRS010B— MAY 1987— REVISED NOVEMBER 1990

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001

24

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT

td(C1-S) STRB from CLKOUT1 (if STRB is present) Q – 15 QQ + 15 ns

td(C2-S) CLKOUT2 to STRB (if STRB is present) – 15 0 15 ns

tsu(A) Address setup hold time before STRB low (see Note 5) Q – 30 ns

th(A) Address hold time after STRB high (see Note 5) Q – 15 ns

tw(SL) STRB low pulse duration (no wait states, see Note 6) 2Q ns

tw(SH) STRB high pulse duration (between consecutive cycles, see Note 6) 2Q ns

tsu(D)W Data write setup time before STRB high (no wait states) 2Q – 45 ns

th(D)W Data write hold time from STRB high Q – 15 Q ns

ten(D) Data bus starts being driven after STRB low (write cycle) 0†ns

tdis(D) Data bus three-state after STRB high (write cycle) QQ+30

†ns

td(MSC) MSC valid from CLKOUT1 –25 0 25 ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.

6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with

no wait states.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

ta(A) Read data access time from address time (read cycle, see Notes 5 and 7) 3Q – 70†ns

tsu(D)R Data read setup time before STRB high 40 ns

th(D)R Data read hold time from STRB high 0 ns

td(SL-R) READY valid after STRB low (no wait states) Q – 40 ns

td(C2H-R) READY valid after CLKOUT2 high Q – 40 ns

th(SL-R) READY hold time after STRB low (no wait states) Q – 5 ns

th(C2H-R) READY hold after CLKOUT2 high Q – 5 ns

td(M-R) READY valid after MSC valid 2Q – 50 ns

th(M-R) READY hold time after MSC valid 0 ns

†Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.

7. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R.

ADVANCE INFORMATION

Contents

Main TMS320 SECOND-GENERATION DIGITAL SIGNAL PROCESSORS TMS320 SECOND-GENERATION PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS TMS320 SECOND-GENERATION DEVICES description introduction Page TMS320 SECOND-GENERATION DEVICES architecture SPRS010B MAY 1987 REVISED NOVEMBER 1990 functional block diagram (TMS320C2x) TMS320 SECOND-GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 Figure 1. Memory Maps 8 (a) Memory Maps After a CNFD Instruction (b) Memory Maps After a CNFP Instruction Program Program Data TMS320 SECOND-GENERATION DEVICES instruction set Page Table 3. TMS320C25 Instruction Set Summary Page Page Page Table 3. TMS320C25 Instruction Set Summary (concluded) Page development support TMS320 Family Development Support Reference Guide Table 4. TMS320 Second-Generation Software and Hardware Support TMS320 Family Development Support Reference Guide TMS320 SECOND-GENERATION documentation support specification overview Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies internal clock option mode, and parallel resonant, with an effective series resistance of 30 external clock option Figure 3. Test Load Circuit Figure 4. Voltage Reference Levels Page switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) Page Page internal clock option or overtone mode, and parallel resonant, with an effective series resistance of 30 Hardware Interfacing to the TMS320C25 external clock option Hardware Interfacing to the TMS320C25 (document number SPRA014A) for details on circuit operation. Figure 4. Test Load Circuit Figure 5. Voltage Reference Levels switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) TMS320C25, TMS320E25 EPROM PROGRAMMING electrical characteristics over specified temperature range (unless otherwise noted) recommended timing requirements for programming, TA = 25C, VCC = 6 V, VPP = 12.5 V (see Notes 14 and 15) Page Page Figure 7. External Clock Option Page switching characteristics over recommended operating conditions (see Notes 3 and 16) timing requirements over recommended operating conditions (see Notes 3 and 16) CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS Page TIMING DIAGRAMS clock timing memory read timing memory write timing one wait-state memory access timing reset timing interrupt timing (TMS32020) interrupt timing (TMS320C25) serial port receive timing serial port transmit timing BIO timing external flag timing BIO timing external flag timing HOLD timing (part A) HOLD timing (part B) HOLD timing (part A) HOLD timing (part B) TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25 TMS320C25FNL (PLCC) reflow soldering precautions no MECHANICAL DATA 68-pin GB grid array ceramic package (TMS32020, TMS320C25) 68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50) WARNING When reflow soldering is required, refer to page 54 for special handling instructions. MECHANICAL DATA 68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only) programming the TMS320E25 EPROM cell Pin Nomenclature (TMS320E25) Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout Page Figure 10. Fast Programming Flowchart Page Page Page Figure 13. EPROM Protect Timing Page Page PACKAGING INFORMATION PACKAGE OPTION ADDENDUM IMPORTANT NOTICE