Texas Instruments TMS320 - page 14

NO.

WORDS

DESCRIPTION INSTRUCTION BIT CODE

MNEMONIC

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

PM

K

TMS320C25

SPRS010B— MAY 1987— REVISED NOVEMBER 1990

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001

14

Table 3. TMS320C25 Instruction Set Summary (continued)

T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

APAC Add P register to accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1

LPH†Load high P register 1 01010011I

LT Load T register 1 00111100I

LTA Load T register and accumulate previous product 1 00111101I

LTD Load T register, accumulate previous product,

and move data 100111111I

LTP†Load T register and store P register in

accumulator 100111110I

LTS†Load T register and subtract previous product 1 01011011I

MAC†Multiply and accumulate 2 01011101I

MACD†Multiply and accumulate with data move 2 01011100I

MPY Multiply (with T register, store product in

P register) 100111000I

MPYA‡Multiply and accumulate previous product 1 00111010I

MPYK Multiply immediate 1 101

MPYS‡ Multiply and subtract previous product 1 00111011I

MPYU‡ Multiply unsigned 1 11001111I

PAC Load accumulator with P register 1 1100111000010100

SPAC Subtract P register from accumulator 1 1100111000010110

SPH‡Store high P register 1 01111101I

SPL‡Store low P register 1 01111100I

SPM†Set P register output shift mode 1 11001110000010

SQRA†Square and accumulate 1 00111001I

SQRS†Square and subtract previous product 1 0 1 0 1 1 0 1 0 I

†These instructions are not included in the TMS320C1x instruction set.

‡These instructions are not included in the TMS32020 instruction set.

Contents

Main TMS320 SECOND-GENERATION DIGITAL SIGNAL PROCESSORS TMS320 SECOND-GENERATION PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS TMS320 SECOND-GENERATION DEVICES description introduction Page TMS320 SECOND-GENERATION DEVICES architecture SPRS010B MAY 1987 REVISED NOVEMBER 1990 functional block diagram (TMS320C2x) TMS320 SECOND-GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 Figure 1. Memory Maps 8 (a) Memory Maps After a CNFD Instruction (b) Memory Maps After a CNFP Instruction Program Program Data TMS320 SECOND-GENERATION DEVICES instruction set Page Table 3. TMS320C25 Instruction Set Summary Page Page Page Table 3. TMS320C25 Instruction Set Summary (concluded) Page development support TMS320 Family Development Support Reference Guide Table 4. TMS320 Second-Generation Software and Hardware Support TMS320 Family Development Support Reference Guide TMS320 SECOND-GENERATION documentation support specification overview Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies internal clock option mode, and parallel resonant, with an effective series resistance of 30 external clock option Figure 3. Test Load Circuit Figure 4. Voltage Reference Levels Page switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) Page Page internal clock option or overtone mode, and parallel resonant, with an effective series resistance of 30 Hardware Interfacing to the TMS320C25 external clock option Hardware Interfacing to the TMS320C25 (document number SPRA014A) for details on circuit operation. Figure 4. Test Load Circuit Figure 5. Voltage Reference Levels switching characteristics over recommended operating conditions (see Note 3 and 8) timing requirements over recommended operating conditions (see Note 3 and 8) TMS320C25, TMS320E25 EPROM PROGRAMMING electrical characteristics over specified temperature range (unless otherwise noted) recommended timing requirements for programming, TA = 25C, VCC = 6 V, VPP = 12.5 V (see Notes 14 and 15) Page Page Figure 7. External Clock Option Page switching characteristics over recommended operating conditions (see Notes 3 and 16) timing requirements over recommended operating conditions (see Notes 3 and 16) CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS Page TIMING DIAGRAMS clock timing memory read timing memory write timing one wait-state memory access timing reset timing interrupt timing (TMS32020) interrupt timing (TMS320C25) serial port receive timing serial port transmit timing BIO timing external flag timing BIO timing external flag timing HOLD timing (part A) HOLD timing (part B) HOLD timing (part A) HOLD timing (part B) TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25 TMS320C25FNL (PLCC) reflow soldering precautions no MECHANICAL DATA 68-pin GB grid array ceramic package (TMS32020, TMS320C25) 68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50) WARNING When reflow soldering is required, refer to page 54 for special handling instructions. MECHANICAL DATA 68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only) programming the TMS320E25 EPROM cell Pin Nomenclature (TMS320E25) Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout Page Figure 10. Fast Programming Flowchart Page Page Page Figure 13. EPROM Protect Timing Page Page PACKAGING INFORMATION PACKAGE OPTION ADDENDUM IMPORTANT NOTICE