Eprom protect, Vih Vil Pgm Vpp Vcc | Texas Instruments TMS320

TMS320E25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

Table 6. TMS320E25 Protect and Verify EPROM Mode Levels

SIGNAL ²

TMS320E25 PIN

TMS27C64 PIN

ROM PROTECT

PROTECT VERIFY

22

20

VIH

VIL

E

42

22

VIH

VIL

G

41

27

VIH

VIH

PGM

VPP

25

1

VPP

VCC

VCC

61,35

28

VCC + 1

VCC

VSS

10, 27, 44

14

VSS

VSS

CLKIN

52

14

VSS

VSS

65

14

VSS

VSS

RS

EPT

24

26

VPP

VPP

Q8-Q1

18-11

11-13, 15-19

Q8 =

Q8 = RBIT

PULSE

A12-A10

40-38

2, 23, 21,

X

X

A9-A7

37, 36, 34

24, 25, 3

X

X

A6

33

4

X

VIL

A5

32

5

X

X

A4

31

6

VIH

X

A3-A0

30-28, 26

7-10

X

X

²In accordance with TMS27C64.

LEGEND;

VIH = TTL high level; VIL = TTL low level; VCC = 5 V ± 0.25 V VPP = 12.5 V ± 0.5 V; X = don't care

PULSE = low-going TTL level pulse; RBIT = ROM protect bit.

EPROM protect

The EPROM protect facility is used to completely disable reading of the EPROM contents to guarantee security of propietary algorithms. This facility is implemented through a unique EPROM cell called the RBIT (EPROM protect bit) cell. Once the contents to be protected are programmed into the EPROM, the RBIT is programmed, disabling access to the EPROM contents and disabling the microprocessor mode on the device. Once programmed, the RBIT can be cleared only by erasing the entire EPROM array with ultraviolet light, thereby maintaining security of the propietary algorithm. Programming the RBIT is accomplished using the EPROM protect cycle, which consists of setting the E, G, PGM, and A4 pins high, VPP and EPT to 2.5 V ± 0.5 V, and pulsing Q8 low. The complete sequence of operations involved in programming the RBIT is shown in the flowchart of Figure 12. The required setups in the figure are detailed in Table 6.

ADVANCE INFORMATION

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63

Image 63

Texas Instruments TMS320E25 Protect and Verify Eprom Mode Levels, Eprom protect, Vih Vil Pgm Vpp Vcc, VSS Clkin EPT VPP

Contents

Description TMS320 SECOND-GENERATION Digital Signal Processors Signals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Wait States for Communication to Slower Off-Chip Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Memory Space Type ArchitectureTMS320 Second-Generation Device Overview Package SECOND-GENERATION Devices Functional block diagram TMS320C2x Memory control TimerScaling shifter 16 ⋅ 16-bit parallel multiplier Memory Maps TMS320 SECOND-GENERATION Devices Interrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary ZAC SUBT²XOR XORK² LTP ² ApacLPH ² LTA Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020 Development support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Documentation support Specification overview Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface Timing RS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock Option VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing IPP1 Eprom ProgrammingSee Notes 14 VPP INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock option Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high MIN TYP MAX Contrast Summary of Electrical SpecificationsClock characteristics and timing Parameter Serial port timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Hold timing Clock timing Timing Diagrams Memory read timing BR, PS, D SReady CLKOUT1 CLKOUT2 Strb Memory write timing MSC One wait-state memory access timing Iack Reset timing Interrupt timing TMS320C25 Interrupt timing TMS32020 Serial port transmit timing Serial port receive timing External flag timing BIO timing PC = N PC = N + Execute Hold timing part aHold Holda Hold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25 Mechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cell EPT VPP Pin Nomenclature TMS320E25VCC EPT Erasure TMS320E25 Programming Mode LevelsSignal Program Read Output Name ² PIN Verify Inhibit Disable Program verify Fast Programming Flowchart Output disable ReadROM protection and verification VSS Clkin EPT VPP TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VIH VIL PGM VPP VCC Rbit Eprom VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCC TMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging Information Important Notice