TMS320E25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

Table 6. TMS320E25 Protect and Verify EPROM Mode Levels

SIGNAL ²

TMS320E25 PIN

TMS27C64 PIN

ROM PROTECT

PROTECT VERIFY

 

 

 

 

 

 

 

 

22

20

VIH

VIL

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

42

22

VIH

VIL

 

 

 

G

 

 

 

 

 

 

 

 

 

 

 

41

27

VIH

VIH

 

PGM

 

 

VPP

25

1

VPP

VCC

 

VCC

61,35

28

VCC + 1

VCC

 

VSS

10, 27, 44

14

VSS

VSS

CLKIN

52

14

VSS

VSS

 

 

 

 

 

 

 

 

65

14

VSS

VSS

 

 

RS

 

 

EPT

24

26

VPP

VPP

Q8-Q1

18-11

11-13, 15-19

Q8 =

 

 

Q8 = RBIT

PULSE

 

 

 

 

 

 

 

A12-A10

40-38

2, 23, 21,

 

X

X

 

 

 

 

 

 

A9-A7

37, 36, 34

24, 25, 3

 

X

X

 

 

 

 

 

 

 

 

 

 

A6

33

4

 

X

VIL

 

 

A5

32

5

 

X

X

 

 

 

 

 

 

 

 

 

A4

31

6

VIH

X

A3-A0

30-28, 26

7-10

 

X

X

²In accordance with TMS27C64.

LEGEND;

VIH = TTL high level; VIL = TTL low level; VCC = 5 V ± 0.25 V VPP = 12.5 V ± 0.5 V; X = don't care

PULSE = low-going TTL level pulse; RBIT = ROM protect bit.

EPROM protect

The EPROM protect facility is used to completely disable reading of the EPROM contents to guarantee security of propietary algorithms. This facility is implemented through a unique EPROM cell called the RBIT (EPROM protect bit) cell. Once the contents to be protected are programmed into the EPROM, the RBIT is programmed, disabling access to the EPROM contents and disabling the microprocessor mode on the device. Once programmed, the RBIT can be cleared only by erasing the entire EPROM array with ultraviolet light, thereby maintaining security of the propietary algorithm. Programming the RBIT is accomplished using the EPROM protect cycle, which consists of setting the E, G, PGM, and A4 pins high, VPP and EPT to 2.5 V ± 0.5 V, and pulsing Q8 low. The complete sequence of operations involved in programming the RBIT is shown in the flowchart of Figure 12. The required setups in the figure are detailed in Table 6.

ADVANCE INFORMATION

POST OFFICE BOX 1443 HOUSTON, TEXAS 77001

63

Page 63
Image 63
Texas Instruments TMS320E25 Protect and Verify Eprom Mode Levels, Eprom protect, Vih Vil Pgm Vpp Vcc, VSS Clkin EPT VPP