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TMS320 SECOND-GENERATION DIGITAL SIGNAL PROCESSORS
TMS320 SECOND-GENERATION
PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS
TMS320 SECOND-GENERATION DEVICES
description
introduction
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TMS320 SECOND-GENERATION DEVICES
architecture
SPRS010B MAY 1987 REVISED NOVEMBER 1990
functional block diagram (TMS320C2x)
TMS320 SECOND-GENERATION DEVICES
SPRS010B MAY 1987 REVISED NOVEMBER 1990
Figure 1. Memory Maps
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(a) Memory Maps After a CNFD Instruction
(b) Memory Maps After a CNFP Instruction
Program Program Data
TMS320 SECOND-GENERATION DEVICES
instruction set
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Table 3. TMS320C25 Instruction Set Summary
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Table 3. TMS320C25 Instruction Set Summary (concluded)
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development support
TMS320 Family Development Support Reference Guide
Table 4. TMS320 Second-Generation Software and Hardware Support
TMS320 Family Development Support Reference Guide
TMS320 SECOND-GENERATION
documentation support
specification overview
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
internal clock option
mode, and parallel resonant, with an effective series resistance of 30
external clock option
Figure 3. Test Load Circuit
Figure 4. Voltage Reference Levels
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switching characteristics over recommended operating conditions (see Note 3 and 8)
timing requirements over recommended operating conditions (see Note 3 and 8)
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internal clock option
or overtone mode, and parallel resonant, with an effective series resistance of 30
Hardware Interfacing to the TMS320C25
external clock option
Hardware Interfacing to the TMS320C25
(document number SPRA014A) for details on circuit operation.
Figure 4. Test Load Circuit
Figure 5. Voltage Reference Levels
switching characteristics over recommended operating conditions (see Note 3 and 8)
timing requirements over recommended operating conditions (see Note 3 and 8)
TMS320C25, TMS320E25
EPROM PROGRAMMING
electrical characteristics over specified temperature range (unless otherwise noted)
recommended timing requirements for programming, TA = 25C, VCC = 6 V, VPP = 12.5 V
(see Notes 14 and 15)
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Figure 7. External Clock Option
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switching characteristics over recommended operating conditions (see Notes 3 and 16)
timing requirements over recommended operating conditions (see Notes 3 and 16)
CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS
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TIMING DIAGRAMS
clock timing
memory read timing
memory write timing
one wait-state memory access timing
reset timing
interrupt timing (TMS32020)
interrupt timing (TMS320C25)
serial port receive timing
serial port transmit timing
BIO timing
external flag timing
BIO timing
external flag timing
HOLD timing (part A)
HOLD timing (part B)
HOLD timing (part A)
HOLD timing (part B)
TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25
TMS320C25FNL (PLCC) reflow soldering precautions
no
MECHANICAL DATA 68-pin GB grid array ceramic package (TMS32020, TMS320C25)
68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50)
WARNING When reflow soldering is required, refer to page 54 for special handling instructions.
MECHANICAL DATA 68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only)
programming the TMS320E25 EPROM cell
Pin Nomenclature (TMS320E25)
Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout
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Figure 10. Fast Programming Flowchart
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Figure 13. EPROM Protect Timing
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PACKAGING INFORMATION
PACKAGE OPTION ADDENDUM
IMPORTANT NOTICE
