Serial Port Timing | Texas Instruments TMS320 instruction

TMS32020

ADVANCE INFORMATION

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

SERIAL PORT TIMING

switching characteristics over recommended operating conditions (see Note 3)

	PARAMETER	MIN	TYP MAX	UNIT

td(CH-DX)	DX valid after CLKX rising edge (see Note 10)		100	ns
td(FL-DX)	DX valid after FSX falling edge (TXM = 0, see Note 10)		50	ns
td(CH-FS)	FSX valid after CLKX rising edge (TXM = 1)		60	ns
NOTES: 3.	Q = 1/4tc(C).
10.	The last occurrence of FSX falling and CLKX rising.

timing requirements over recommended operating conditions (see Note 3)

		MIN	NOM	MAX	UNIT

t	Serial port clock (CLKX/CLKR) cycle time	390		20 000²	ns
c(SCK)
tf(SCK)	Serial port clock (CLKX/CLKR) fall time			50³	ns
t	Serial port clock (CLKX/CLKR) rise time			50³	ns
r(SCK)
tw(SCK)	Serial port clock (CLKX/CLKR) low pulse duration (see Note 11)	150		12 000	ns
tw(SCK)	Serial port clock (CLKX/CLKR) high pulse duration (see Note 11)	150		12 000	ns
tsu(FS)	FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)	20			ns
th(FS)	FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)	20			ns
tsu(DR)	DR setup time before CLKR falling edge	20			ns
th(DR)	DR hold time after CLKR falling edge	20			ns

²Value derived from characterization data; minimum fsx at test = 825 kHz. ³ Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

11. The duty cycle of the serial port clock must be within 40-60%.

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Image 26

Texas Instruments TMS320 specifications Serial Port Timing

Contents

TMS320 SECOND-GENERATION Digital Signal Processors Description Function PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Memory Space Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Wait States for Communication to Slower Off-Chip Package ArchitectureTMS320 Second-Generation Device Overview Type Functional block diagram TMS320C2x SECOND-GENERATION Devices 16 ⋅ 16-bit parallel multiplier TimerScaling shifter Memory control TMS320 SECOND-GENERATION Devices Memory Maps Multiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary XORK² SUBT²XOR ZAC LTA ApacLPH ² LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product Notification Development support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Specification overview Documentation support Parameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX Unit Hold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit External Clock Option Clkin VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing VPP Eprom ProgrammingSee Notes 14 IPP1 MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr Internal Clock Option External clock option CLKOUT1, CLKOUT2 Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Parameter Contrast Summary of Electrical SpecificationsClock characteristics and timing MIN TYP MAX Hold timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Serial port timing Timing Diagrams Clock timing Ready Memory read timingBR, PS, D S Memory write timing CLKOUT1 CLKOUT2 Strb One wait-state memory access timing MSC Reset timing Iack Interrupt timing TMS32020 Interrupt timing TMS320C25 Serial port receive timing Serial port transmit timing BIO timing External flag timing PC = N PC = N + Holda Hold timing part aHold Execute Holda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautions Parameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verification EPT Pin Nomenclature TMS320E25VCC EPT VPP Program Read Output Name ² PIN Verify Inhibit Disable TMS320E25 Programming Mode LevelsSignal Erasure Fast Programming Flowchart Program verify ROM protection and verification Output disableRead VIH VIL PGM VPP VCC TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VSS Clkin EPT VPP Eprom Rbit VIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS TMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25 Important Notice