TdC1-S From Clkout if Is present | Texas Instruments TMS320 specification

TMS320C25-50

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER

MIN

TYP

MAX

UNIT

td(C1-S)

from CLKOUT (if

is present)

Q ± 5

Q + 3

ns

STRB

STRB

td(C2-S)

CLKOUT2 to

(if

is present)

± 2

5

ns

STRB

STRB

tsu(A)

Address setup time before

low (see Note 5)

Q ± 11

ns

STRB

tn(A)

Address hold time after

high (see Note 5)

Q ± 4

ns

STRB

tw(SL)

low pulse duration (no wait states, see Note 6)

2Q ± 5

2Q + 2

ns

STRB

t

high pulse duration (between consecutive cycles, see Note 6)

2Q ± 2

2Q + 5²

ns

STRB

w(SH)

tsu(D)W

Data write setup time before

high (no wait)

2Q ± 17

ns

STRB

th(D)W

Data write hold time from

high

Q ± 5

ns

STRB

t

Data bus starts being driven after

low (write)

0 ²

ns

STRB

en(D)

t

Data bus high-impedance state after

high, (write)

Q

Q + 15²

ns

STRB

dis(D)

td(MSC)

valid from CLKOUT1

±1

9

ns

MSC

²Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C)

5.A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as ªaddressº.

6.Delay between CLKOUT1, CLKOUT2, and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states.

timing requirements over recommended operating conditions (see Note 3)

MIN

NOM

MAX

UNIT

ta(A)

Read data access time from address time (see Notes 5 and 7)

3Q ± 30

ns

tsu(D)R

Data read setup time before

high

19

ns

STRB

th(D)R

Data read hold time from

high

0

ns

STRB

td(SL-R)

READY valid after

low (no wait states)

Q ± 21

ns

STRB

td(C2H-R)

READY valid after CLKOUT2 high

Q ± 21

ns

th(SL-R)

READY hold time after

low (no wait states)

Q ± 1

ns

STRB

th(C2H-R)

READY valid after CLKOUT2 high

Q ± 1

ns

td(M-R)

READY valid after

valid

2Q ± 24

ns

MSC

th(M-R)

READY hold time after

valid

0

ns

MSC

NOTES: 3. Q = 1/4 tc(C)

5.A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as ªaddressº.

7. Read data access time is defined as ta(A) = tsu(A) + tw(SL) ± tsu(D)R.

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37

Image 37

Texas Instruments TMS320 specifications TdC1-S From Clkout if Is present

Contents

Description TMS320 SECOND-GENERATION Digital Signal Processors PGA and PLCC/CER-QUAD PIN Assignments Signals DefinitionFunction PIN Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-Chip TMS320 Second-Generation Device Overview ArchitecturePackage Type SECOND-GENERATION Devices Functional block diagram TMS320C2x Scaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory control Memory Maps TMS320 SECOND-GENERATION Devices External interface Interrupts and subroutinesMultiprocessing Instruction set Repeat featureAddressing modes Symbol Definition Instruction SymbolsInstruction set summary TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZAC LPH ² ApacLTA LTP ² Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020 Development support Software Tools Part Number TMS320 Second-Generation Software and Hardware SupportHardware Tools Part Number Documentation support Specification overview MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP§ MAX Unit Internal clock option Clock Characteristics and TimingExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface Timing Hold Timing RS, INT, BIO, and XF TimingHold Holda Serial Port Timing MP/MC IOH INT Clkin / Clkx / ClkrTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock Option VOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1 CLKIN, CLKX, Clkr INT0 INT2 VIHMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock option Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAX RS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timing Clock timing Timing Diagrams BR, PS, D S Memory read timingReady CLKOUT1 CLKOUT2 Strb Memory write timing MSC One wait-state memory access timing Iack Reset timing Interrupt timing TMS320C25 Interrupt timing TMS32020 Serial port transmit timing Serial port receive timing External flag timing BIO timing PC = N PC = N + Hold Hold timing part aHolda Execute CLKOUT1 CLKOUT2 Hold timing part BHolda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25 Pin GB grid array ceramic package TMS32020, TMS320C25 Mechanical DataParameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cell VCC Pin Nomenclature TMS320E25EPT EPT VPP Signal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable Erasure Program verify Fast Programming Flowchart Read Output disableROM protection and verification Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPP Rbit Eprom VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCC TMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging Information Important Notice