Xilinx ML310 manual Summary of Virtex-II Pro Features

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Chapter 1

Introduction to Virtex-II Pro, ISE, and EDK

Virtex-II Pro

The Virtex-II Pro Platform FPGA solution is the most technically sophisticated silicon and software product development in the history of the programmable logic industry. The goal was to revolutionize system architecture “from the ground up.” To achieve that objective, the best circuit engineers and system architects from IBM, Mindspeed, and Xilinx co- developed the world's most advanced Platform FPGA silicon product. Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled new system architecture paradigm.

The result is the first Platform FPGA solution capable of implementing high performance system-on-a-chip designs previously the exclusive domain of custom ASICs, yet with the flexibility and low development cost of programmable logic. The Virtex-II Pro family marks the first paradigm change from programmable logic to programmable systems, with profound implications for leading-edge system architectures in networking applications, deeply embedded systems, and digital signal processing systems. It allows custom user-defined system architectures to be synthesized, next-generation connectivity standards to be seamlessly bridged, and complex hardware and software systems to be co- developed rapidly with in-system debug at system speeds. Together, these capabilities usher in the next programmable logic revolution.

Summary of Virtex-II Pro Features

The Virtex-II Pro has an impressive collection of both programmable logic and hard IP that has historically been the domain of the ASICs.

High-performance Platform FPGA solution including

Up to twenty-four RocketIO™ embedded multi-gigabit transceiver blocks (based on Mindspeed's SkyRail™ technology)

Up to four IBM® PowerPC™ RISC processor blocks

Based on Virtex™-II Platform FPGA technology

Flexible logic resources, up to 125,136 Logic Cells

SRAM-based in-system configuration

Active Interconnect™ technology

SelectRAM™ memory hierarchy

Up to 556 Dedicated 18-bit x 18-bit multiplier blocks

High-performance clock management circuitry

SelectIO™-Ultra technology

Digitally Controlled Impedance (DCI) I/O

ML310 User Guide

www.xilinx.com

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UG068 (v1.01) August 25, 2004

1-800-255-7778

 

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Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricIntroduction to Virtex-II Pro, ISE, and EDK Foundation FeaturesFoundation ISE Design EntryFoundation ISE Implementation and ConfigurationSynthesis Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryU37 DDR SignalingDDR Memory Expansion DDRA2 DDRDQS02 DDRDQ31 RS-232 on the ML310 Signaling Standards of RS-232Serial Port Fpga Uart Introduction to Serial PortsBoard Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30Parallel Cable IV Interface System ACE Jtag Configuration InterfaceGpio LEDs and LCD 8LEDs and LCD Connectivity U37 Name U36 UCF Signal Name Translator U37 J13 U35Gpio LED Interface Gpio LCD InterfaceBuffer U33 J13 CPU Debug and CPU TraceCPU Debug Description 9Combined Trace/Debug Connector Pinout CPU Debug Connection to XC2VP30 CPU Debug Connector PinoutPCI Bus ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 125.0V Secondary PCI Bus Information Device Name Vendor ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor Device Name Bus12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 17Type of Gpio Available on Header J5 ALi Gpio Types Number GPIO, connector J5System Management Bus SMBus AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus on ML310 Board IIC/SMBus SignalingIIC/SMBus Interface Introduction to IIC/SMBus22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingPush Buttons Push Buttons, Switches, Front Panel Interface and JumpersSPI Addressing CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 J10 J11 Coupling JumpersVoltage Jumper MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorContact Order ML310 PM Utility PinsAdapter Board PM Connectors PM1 User I/O ML310 PM User I/O PinsPM1 Power and Ground PM2 Power and GroundRXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5