
Board Hardware
R
a UART usable with any member of the
The
Figure 2-5 shows the RS-232 connectivity from the XC2VP30 to the DTK adapter.
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| USE A |
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| J4 | TO DB9 PLUG CABLE. |
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U37 | U7 |
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| 1 |
| 2 |
| 1 | CD |
UART0_TXD | 11 DIN1 |
| 14 | COM0_TXD_N |
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| DSR | ||
DOUT1 | 3 |
| 4 | 6 |
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UART0_RTS_N | 10 DIN2 | DOUT2 | 7 | COM0_RTS |
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UART0_RXD | 12 ROUT1 | RIN1 | 13 | COM0_RXD_N |
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| RTS | 7 |
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UART0_CTS_N | 9 ROUT2 | RIN2 | 8 | COM0_CTS | 5 |
| 6 |
| 3 | TX |
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| 7 |
| 8 | CTS | 8 |
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| VCC3V3 |
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| 4 | DTR | ||
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| RI | |||
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| 9 |
| 10 | 9 |
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| 5 | GND | ||
| 1 C1+ | VCC16 |
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C330 |
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| C326 | HEADER2X5 |
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0.1UF |
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| RS232 DTE PINOUT | |
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| 2 |
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| F/F NULL MODEL CABLE. | |||
| 4 C2+ |
| 6 | VCC3V3 |
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C331 |
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| C327 |
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0.1UF |
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| 0.1UF | C313 |
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| 0.1UF |
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| 5 C2- | GND15 |
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XC2VP30 | MAX3232 |
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Figure 2-5: FPGA UART and RS-232 Connectivity
Table
Table
UCF Signal | XC2VP30 Pin | Schem Signal | 10 pin Header | DTK Adapter |
Name | (U37) | Name | (J4) | (DB9) |
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uart1_ctsn | B10 | UART0_CTS | 6 | 8 |
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uart1_rtsn | G14 | UART0_RTS | 4 | 7 |
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uart1_sin | F14 | UART0_RXD | 3 | 2 |
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uart1_sout | F12 | UART0_TXD | 5 | 3 |
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System ACE CF Controller
Board Bring-Up
System ACE is the primary means of configuring the XC2VP30 on the ML310 board.Configuration of XC2VP30 is accomplished using the JTAG interface. System ACE sits between the JTAG connector and the XC2VP30, and passes the JTAG signals back and forth between the two. However, when System ACE is configuring the XC2VP30, it takes control of the JTAG signals in order to configure the XC2VP30.
ML310 User Guide | www.xilinx.com | 27 |
UG068 (v1.01) August 25, 2004 |
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