Xilinx ML310 manual System ACE CF Controller, Board Bring-Up

Page 27

Board Hardware

R

a UART usable with any member of the Virtex-II Pro device family. Please review the EDK Processor IP Reference Guide for more details.

The RS-232 port directly connected to the XC2VP30 is accessible by a 10 pin header(J4). An RS-232 mini-cable adapter included with the ML310 converts J4, 10 pin header, to a DB9 male connector. The adapter is a standard DTK/Intel IDC-10 to DB9 Male. The FPGA RS- 232 port on the ML310 is wired as a DTE and meets the EIA/TIA-574standard

Figure 2-5shows the RS-232 connectivity from the XC2VP30 to the DTK adapter.

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USE A DTK-PINOUT IDC10

 

 

 

 

 

 

 

J4

TO DB9 PLUG CABLE.

 

 

 

 

 

 

 

 

 

 

 

 

U37

U7

 

 

 

1

 

2

 

1

CD

UART0_TXD

11 DIN1

 

14

COM0_TXD_N

 

 

 

DSR

DOUT1

3

 

4

6

 

UART0_RTS_N

10 DIN2

DOUT2

7

COM0_RTS

 

 

2

RX

UART0_RXD

12 ROUT1

RIN1

13

COM0_RXD_N

 

 

RTS

7

 

UART0_CTS_N

9 ROUT2

RIN2

8

COM0_CTS

5

 

6

 

3

TX

 

 

 

 

 

7

 

8

CTS

8

 

 

 

 

 

VCC3V3

 

 

4

DTR

 

 

 

 

 

 

 

RI

 

 

 

 

 

9

 

10

9

 

 

 

 

 

 

 

 

5

GND

 

1 C1+

VCC16

 

 

 

 

 

 

 

 

 

 

 

 

 

C330

 

 

 

C326

HEADER2X5

 

 

 

0.1UF

 

 

 

0.1UF

 

 

 

 

RS232 DTE PINOUT

 

3 C1-

 

2

 

 

 

 

 

CONNECTS TO PC WITH

 

V+

 

 

 

 

 

F/F NULL MODEL CABLE.

 

4 C2+

 

6

VCC3V3

 

 

 

 

 

 

V-

 

 

 

 

 

 

 

C331

 

 

 

C327

 

 

 

 

 

 

0.1UF

 

 

 

0.1UF

C313

 

 

 

 

 

 

 

 

 

 

0.1UF

 

 

 

 

 

 

5 C2-

GND15

 

 

 

 

 

 

 

XC2VP30

MAX3232

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG068_5_32_080204

 

 

 

 

 

Figure 2-5:FPGA UART and RS-232 Connectivity

Table 2-3shows the RS-232 connections to the XCV2VP30 FPGA.

Table 2-3:FPGA RS-232 Connections

UCF Signal

XC2VP30 Pin

Schem Signal

10 pin Header

DTK Adapter

Name

(U37)

Name

(J4)

(DB9)

 

 

 

 

 

uart1_ctsn

B10

UART0_CTS

6

8

 

 

 

 

 

uart1_rtsn

G14

UART0_RTS

4

7

 

 

 

 

 

uart1_sin

F14

UART0_RXD

3

2

 

 

 

 

 

uart1_sout

F12

UART0_TXD

5

3

 

 

 

 

 

System ACE CF Controller

Board Bring-Up

System ACE is the primary means of configuring the XC2VP30 on the ML310 board.Configuration of XC2VP30 is accomplished using the JTAG interface. System ACE sits between the JTAG connector and the XC2VP30, and passes the JTAG signals back and forth between the two. However, when System ACE is configuring the XC2VP30, it takes control of the JTAG signals in order to configure the XC2VP30.

ML310 User Guide

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UG068 (v1.01) August 25, 2004

1-800-255-7778

 

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Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricIntroduction to Virtex-II Pro, ISE, and EDK Foundation FeaturesFoundation ISE Design EntryImplementation and Configuration SynthesisFoundation ISE Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryDDR Signaling DDR Memory ExpansionU37 DDRA2 DDRDQS02 DDRDQ31 RS-232 on the ML310 Signaling Standards of RS-232Serial Port Fpga Uart Introduction to Serial PortsBoard Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30System ACE Jtag Configuration Interface Gpio LEDs and LCDParallel Cable IV Interface 8LEDs and LCD Connectivity U37 Name U36 UCF Signal Name Translator U37 J13 U35Gpio LED Interface Gpio LCD InterfaceCPU Debug and CPU Trace CPU Debug DescriptionBuffer U33 J13 9Combined Trace/Debug Connector Pinout CPU Debug Connector Pinout PCI BusCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 125.0V Secondary PCI Bus Information Device Name Vendor ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor Device Name Bus12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus SMBus17Type of Gpio Available on Header J5 ALi Gpio Types Number AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus on ML310 Board IIC/SMBus SignalingIIC/SMBus Interface Introduction to IIC/SMBus22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingPush Buttons, Switches, Front Panel Interface and Jumpers SPI AddressingPush Buttons CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 Jumpers Voltage JumperJ10 J11 Coupling MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorML310 PM Utility Pins Adapter Board PM ConnectorsContact Order PM1 User I/O ML310 PM User I/O PinsPM1 Power and Ground PM2 Power and GroundRXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5