Xilinx ML310 manual CPU Debug and CPU Trace, CPU Debug Description, Buffer U33 J13

Xilinx ML310 manual DDR Memory, Board Hardware Xilinx ML310 manual DDR Signaling, DDR Memory Expansion, U37 Xilinx ML310 manual DDRA2 Xilinx ML310 manual DDRDQS02 Xilinx ML310 manual DDRDQ31 Xilinx manual Serial Port Fpga Uart, Introduction to Serial Ports, Signaling Standards of RS-232, RS-232 on the ML310 Xilinx ML310 manual System ACE CF Controller, Board Bring-Up Xilinx ML310 manual Non-Volatile Storage, XC2VP30 Connectivity Xilinx ML310 manual Jtag Connection to XC2VP30, 6JTAG Connections to the XC2VP30 and System ACE Xilinx ML310 manual Gpio LEDs and LCD, Parallel Cable IV Interface, System ACE Jtag Configuration Interface Xilinx ML310 manual 8LEDs and LCD Connectivity Xilinx ML310 manual Gpio LED Interface, Gpio LCD Interface, U37 Name U36, UCF Signal Name Translator U37 J13 U35 Xilinx ML310 manual CPU Debug and CPU Trace, CPU Debug Description, Buffer U33 J13 Xilinx ML310 manual 9Combined Trace/Debug Connector Pinout Xilinx ML310 manual PCI Bus, CPU Debug Connector Pinout, CPU Debug Connection to XC2VP30 Xilinx manual ML310 Embedded Development Platform Xilinx ML310 manual PCI Bus and Device Connectivity Xilinx ML310 manual Pciinta Pciintb Pciintc Xilinx ML310 manual Pcipar Pcippar Pcirstn Pciprstn Xilinx ML310 ALi South Bridge Interface, M1535D+, U15, 113.3V Primary PCI Bus Information Device Vendor, Device Name Bus Xilinx ML310 manual Parallel Port Interface, connector assembly P1, 12ALi South Bridge Interface, M1535D+, U15 Xilinx ML310 manual Serial Port Interface, connector assembly P1 Xilinx ML310 manual USB, connector assembly J3 Xilinx ML310 manual IDE, connectors J15 and J16 Xilinx ML310 GPIO, connector J5, System Management Bus SMBus, 17Type of Gpio Available on Header J5 ALi Gpio Types Number Xilinx ML310 manual AC97 Audio, 19Audio Jacks, J1 and J2 Signal name Description Xilinx ML310 manual PS/2 Keyboard/Mouse Interface, connector P2, Flash ROM, U4 Xilinx ML310 manual Intel GD82559, U11, 10/100 Ethernet Controller, Intel GD82559 Ethernet Controller Xilinx manual IIC/SMBus Interface, Introduction to IIC/SMBus, IIC/SMBus Signaling, IIC/SMBus on ML310 Board Xilinx ML310 manual 22shows the Fpga connections to all SMBus and IIC devices Xilinx ML310 manual 14SMBus and IIC Block Diagram Xilinx ML310 manual Serial Peripheral Interface SPI, SPI Signaling Xilinx ML310 manual Push Buttons, Switches, Front Panel Interface and Jumpers, SPI Addressing Xilinx ML310 manual System ACE Configuration Dipswitch, SW3, CPU Reset, SW2 Xilinx ML310 manual Front Panel Interface Connector, J23, 16SW3 SysACE CFG Switch Detail Xilinx ML310 manual SYACECFGA0
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Board Hardware

R

The three GPIO signals configured as outputs only are used as control signals that allows the user to read/write the LCD character display in conjunction with the eight LCD data signals defined earlier in Table 2-7. Please review the AND491GST LCD display data sheet located on the ML310 CDROM for more detailed information.

Table 2-8shows the control signal connections for the GPIO LCD from the FPGA to U33.

Table 2-8:GPIO LCD Control Signal Connections from FPGA to U33

UCF Signal Name

XC2VP30 Pin

Schem Signal

LVC244

LCD I/F

(U37)

Name

Buffer (U33)

(J13)

 

 

 

 

 

 

FPGA_LCD_E

C21

FPGA_LCD_E

13

6

 

 

 

 

 

FPGA_LCD_RS

J17

FPGA_LCD_RS

11

4

 

 

 

 

 

FPGA_LCD_RW

H17

FPGA_LCD_RW

15

5

 

 

 

 

 

CPU Debug and CPU Trace

The ML310 board includes two CPU debugging interfaces, the CPU Debug (J12 header) and the Combined CPU Trace and Debug (P8 mictor) connector.

These connectors can be used in conjunction with third party tools, or in some cases the Xilinx Parallel Cable IV, to debug software as it runs on the processor.The PowerPCTM 405 CPU core includes dedicated debug resources that support a variety of debug modes for debugging during hardware and software development. These debug resources include:

•Internal debug mode for use by ROM monitors and software debuggers

•External debug mode for use by JTAG debuggers

•Debug wait mode, which allows the servicing of interrupts while the processor appears to be stopped

•Real-time trace mode, which supports event triggering for real-time tracing

Debug modes and events are controlled using debug registers in the processor. The debug registers are accessed either through software running on the processor or through the JTAG port. The debug modes, events, controls, and interfaces provide a powerful combination of debug resources for hardware and software development tools. The JTAG port interface supports the attachment of external debug tools, such as the ChipScopeTM Integrated Logic Analyzer, a powerful tool providing logic analyzer capabilities for signals inside an FPGA, without the need for expensive external instrumentation. Using the JTAG test access port, a debug tool can single-step the processor and examine the internal processor state to facilitate software debugging. This capability complies with the IEEE 1149.1 specification for vendor-specific extensions and is, therefore, compatible with standard JTAG hardware for boundary-scan system testing.(1)

CPU Debug Description

External-debug mode can be used to alter normal program execution. It provides the ability to debug system hardware as well as software. The mode supports multiple setting breakpoints, as well as monitoring processor status. Access to processor resources is provided through the CPU Debug port.(2)

1.http://www.support.xilinx.com/ PowerPC Architecture - Debug (JTAG, Trace), Sept. 12, 2002

2.Virtex-II Pro Platform FPGA Documentation - Volume 2(a): PPC405 User Manual, March 2002 Release, p. 537.

ML310 User Guide

www.xilinx.com

33

UG068 (v1.01) August 25, 2004

1-800-255-7778

 

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Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricFoundation ISE Foundation FeaturesDesign Entry Introduction to Virtex-II Pro, ISE, and EDKImplementation and Configuration SynthesisFoundation ISE Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryDDR Signaling DDR Memory ExpansionU37 DDRA2 DDRDQS02 DDRDQ31 Serial Port Fpga Uart Signaling Standards of RS-232Introduction to Serial Ports RS-232 on the ML310Board Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30System ACE Jtag Configuration Interface Gpio LEDs and LCDParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LED Interface UCF Signal Name Translator U37 J13 U35Gpio LCD Interface U37 Name U36CPU Debug and CPU Trace CPU Debug DescriptionBuffer U33 J13 9Combined Trace/Debug Connector Pinout CPU Debug Connector Pinout PCI BusCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 113.3V Primary PCI Bus Information Device Vendor ALi South Bridge Interface, M1535D+, U15Device Name Bus 125.0V Secondary PCI Bus Information Device Name Vendor12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus SMBus17Type of Gpio Available on Header J5 ALi Gpio Types Number AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus Interface IIC/SMBus SignalingIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingPush Buttons, Switches, Front Panel Interface and Jumpers SPI AddressingPush Buttons CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 Jumpers Voltage JumperJ10 J11 Coupling MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorML310 PM Utility Pins Adapter Board PM ConnectorsContact Order PM1 Power and Ground ML310 PM User I/O PinsPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5
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