
R
Chapter 1: Introduction to
Table
Device | 2VP2 | 2VP4 | 2VP7 | 2VP20 | 2VP30 | 2VP40 | 2VP50 | 2VP70 | 2VP100 | 2VP125 |
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Logic Cells | 3,168 | 6,768 | 11,088 | 20,880 | 30,816 | 43,632 | 53,136 | 74,448 | 99,216 | 125,136 |
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PPC405 | 0 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 4 |
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MGTs | 4 | 4 | 8 | 8 | 8 | 12 | 16 | 20 | 20 | 24 |
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BRAM | 216 | 504 | 792 | 1,584 | 2,448 | 3,456 | 4,176 | 5,904 | 7,992 | 10,008 |
(Kbits) |
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Xtreme | 12 | 28 | 44 | 88 | 136 | 192 | 232 | 328 | 444 | 556 |
Multipliers |
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PowerPC™ 405 Core
•Embedded 300+ MHz Harvard architecture core
•Low power consumption: 0.9 mW/MHz
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•Hardware multiply/divide unit
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•16 KB
•16 KB
•Memory Management Unit (MMU)
♦
♦Variable page sizes (1 KB to 16 MB)
•Dedicated
•Supports IBM CoreConnect™ bus architecture
•Debug and trace support
•Timer facilities
RocketIO 3.125 Gb/s Transceivers
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•80 Gb/s duplex data rate (16 channels)
•Monolithic clock synthesis and clock recovery (CDR)
•Fibre Channel, Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI), and
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•8B /10B encoder and decoder
• 50Ω /75Ω
•Programmable comma detection
•Channel bonding support (two to sixteen channels)
•Rate matching via insertion/deletion characters
12 | www.xilinx.com | ML310 User Guide |
| UG068 (v1.01) August 25, 2004 |