Xilinx ML310 Intel GD82559, U11, 10/100 Ethernet Controller, Intel GD82559 Ethernet Controller

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Chapter 2: ML310 Embedded Development Platform

Table 2-21:ALi M1535 Flash Memory Interface

Schem Net Name

M1535D+

AM29F040B

Description

(U15)

(U4)

 

 

 

 

 

 

ROM_A18

T15

9

 

 

 

 

 

ROM_A17

U15

6

 

 

 

 

 

ROM_A16

V15

10

 

 

 

 

 

ROM_A15

W15

11

 

 

 

 

 

ROM_A14

T16

5

 

 

 

 

 

ROM_A13

U16

4

 

 

 

 

 

ROM_A12

V16

12

 

 

 

 

 

ROM_A11

W16

1

 

 

 

 

 

ROM_A10

Y16

31

 

 

 

 

Flash Addresses

ROM_A9

R17

2

 

 

 

 

ROM_A8

T17

3

 

 

 

 

 

ROM_A7

U17

13

 

 

 

 

 

ROM_A6

V17

14

 

 

 

 

 

ROM_A5

W17

15

 

 

 

 

 

ROM_A4

Y17

16

 

 

 

 

 

ROM_A3

V18

17

 

 

 

 

 

ROM_A2

W18

18

 

 

 

 

 

ROM_A1

Y18

19

 

 

 

 

 

ROM_A0

V19

20

 

 

 

 

 

Intel GD82559, U11, 10/100 Ethernet Controller

Intel GD82559 Ethernet Controller

The GD82559 10/100 Mbps Fast Ethernet controller with an integrated 10/100 Mbps physical layer device for PCI board LAN designs. It is designed for use in Network Interface Cards (NICs), PC LAN On Motherboard (LOM) designs, embedded systems and networking system products. It consists of both the Media Access Controller (MAC) and the physical layer (PHY) interface combined into a single component solution. The 82559 can operate in either full duplex or half duplex mode.The GD82559 also includes an interface to a serial (4-pin) EEPROM and a parallel interface to a 128 Kilobyte Flash memory. The EEPROM provides power-on initialization for hardware and software configuration parameters.

The ML310 board utilizes the 82559 10/100 Ethernet capability via FPGA PCI host bridge accesses over the PCI Bus. The 82559 is only accessible over the PCI bus, this includes programming of its power-on initialization EEPROM. The GD82559’s EEPROM is pre programmed on each ML310 with a unique MAC address. The ML310 MAC address is identified by the mylar label near the RJ45 connector labeled "ETH0 MAC ADDR". Please

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ML310 User Guide

 

1-800-255-7778

UG068 (v1.01) August 25, 2004

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Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProFoundation Features Foundation ISEDesign Entry Introduction to Virtex-II Pro, ISE, and EDKImplementation and Configuration SynthesisFoundation ISE Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareDDR Signaling DDR Memory ExpansionU37 DDRA2 DDRDQS02 DDRDQ31 Signaling Standards of RS-232 Serial Port Fpga UartIntroduction to Serial Ports RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACESystem ACE Jtag Configuration Interface Gpio LEDs and LCDParallel Cable IV Interface 8LEDs and LCD Connectivity UCF Signal Name Translator U37 J13 U35 Gpio LED InterfaceGpio LCD Interface U37 Name U36CPU Debug and CPU Trace CPU Debug DescriptionBuffer U33 J13 9Combined Trace/Debug Connector Pinout CPU Debug Connector Pinout PCI BusCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn ALi South Bridge Interface, M1535D+, U15 113.3V Primary PCI Bus Information Device VendorDevice Name Bus 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus SMBus17Type of Gpio Available on Header J5 ALi Gpio Types Number 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIIC/SMBus Signaling IIC/SMBus InterfaceIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPIPush Buttons, Switches, Front Panel Interface and Jumpers SPI AddressingPush Buttons System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 Jumpers Voltage JumperJ10 J11 Coupling ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorML310 PM Utility Pins Adapter Board PM ConnectorsContact Order ML310 PM User I/O Pins PM1 Power and GroundPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5