Xilinx ML310 manual Serial Port Interface, connector assembly P1

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Chapter 2: ML310 Embedded Development Platform

Table 2-13shows the ALi Parallel Port connections to P1, DB25.

Table 2-13:ALi South Bridge Parallel Port pinout P1 (DB25)

Signal Name

P1 (DB25)

Description

Pin No.

 

 

 

 

 

STROBE_N

1

Strobe

 

 

 

D0

2

Data Bit 0

 

 

 

D1

3

Data Bit 1

 

 

 

D2

4

Data Bit 2

 

 

 

D3

5

Data Bit 3

 

 

 

D4

6

Data Bit 4

 

 

 

D5

7

Data Bit 5

 

 

 

D6

8

Data Bit 6

 

 

 

D7

9

Data Bit 7

 

 

 

ACK_N

10

Acknowledge

 

 

 

BUSY

11

Busy

 

 

 

PEND

12

Paper End

 

 

 

SELECT

13

Select

 

 

 

AUTOFD_N

14

Autofeed

 

 

 

ERROR_N

15

Error

 

 

 

INIT_N

16

Initialize

 

 

 

SLCTIN_N

17

Select In

 

 

 

GND

18, 19, 20,

Ground

 

21, 22, 23,

 

 

24, 25

 

 

 

 

Serial Port Interface, connector assembly P1

In addition to the serial port accessible via the XC2VP30 FPGA, the ALi M1535D+ provides access over the PCI Bus to two serial ports. The ALi M1535D+ employs 16450/16550 Compatible UARTs with Send/Receive16-byte FIFOs. The two Serial ports are connected to the ALi M1535D+ device via two male DB9 connectors (P1). The DB9 connectors are configured as DTE interfaces and meet the EIA/TIA-574standard.

The DB9 male connectors are labeled Serial Port A and B in the ML310 schematics. The DB9 connectors are part of the P1 connector assembly. Please note that Serial Port B is located adjacent to the PS/2 connector where COM1 in a legacy PC is traditionally located. The two DB9 serial port connectors are labeled on the ML310 board silk-screen near the P1 connector assembly. Please review the ALi M1535D+ Data sheets for more detailed information.

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ML310 User Guide

 

1-800-255-7778

UG068 (v1.01) August 25, 2004

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Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProDesign Entry Foundation FeaturesFoundation ISE Introduction to Virtex-II Pro, ISE, and EDKImplementation and Configuration SynthesisFoundation ISE Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareDDR Signaling DDR Memory ExpansionU37 DDRA2 DDRDQS02 DDRDQ31 Introduction to Serial Ports Signaling Standards of RS-232Serial Port Fpga Uart RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACESystem ACE Jtag Configuration Interface Gpio LEDs and LCDParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LCD Interface UCF Signal Name Translator U37 J13 U35Gpio LED Interface U37 Name U36CPU Debug and CPU Trace CPU Debug DescriptionBuffer U33 J13 9Combined Trace/Debug Connector Pinout CPU Debug Connector Pinout PCI BusCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn Device Name Bus ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus SMBus17Type of Gpio Available on Header J5 ALi Gpio Types Number 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIntroduction to IIC/SMBus IIC/SMBus SignalingIIC/SMBus Interface IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPIPush Buttons, Switches, Front Panel Interface and Jumpers SPI AddressingPush Buttons System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 Jumpers Voltage JumperJ10 J11 Coupling ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorML310 PM Utility Pins Adapter Board PM ConnectorsContact Order PM2 Power and Ground ML310 PM User I/O PinsPM1 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5
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