Xilinx manual ML310 Embedded Development Platform

Page 36

R

Chapter 2: ML310 Embedded Development Platform

Arbiter IP. Please see the EDK Processor IP Reference Guide for more information about the EDK IP mentioned in this section.

The FPGA is responsible generating the PCI RST signal as well as the PCI CLK signal. The FPGA fabric is used to generate six PCI Clocks that drive each of the PCI devices/slots shown in the Figure 2-11. All six PCI Clock outputs are length matched. Since the FPGA generates all PCI Clocks, the downstream PCI devices have no clock input prior to or during FPGA configuration therefore, PCI Reset should be de-asserted after the PCI CLK has stabilized. Please review the PCI Local Bus Specification, Revision 2.2 for more detailed information.

The on-board 33MHz/32 bit PCI Bus is connected to three fixed PCI devices that are part of the ML310 board. These devices are listed below and more information on the devices can be found in the following sections as well their data sheets on the ML310 CDROM

Texas Instruments, TI2250, PCI-to-PCI Bridge

Intel, GD82559, 10/100 PCI Ethernet NIC.

Ali, M1535D+, PCI South Bridge

In addition to the three fixed PCI devices, there are a total of four 33MHz/32 Bit PCI slots available for use. For more information on the PCI slot pinouts, refer to the PCI Local Bus Specification, Revision 2.2 and the ML310 schematics.

2 - 3.3V Keyed PCI Add In Card Slots (P5 and P3)

2 - 5.0V Keyed PCI Add In Card Slots (P6 and P4)

Note: The 5.0V PCI slots differ from the 3.3V slots. See the Important Instructions sheet (PN 0402263) packaged with the ML310 kit before using Universal PCI add-in cards with the ML310 board.

Figure 2-11shows the connectivity of the PCI bus and PCI devices. For more information on the PCI slot pinouts, refer to the PCI 2.2 Specification or review the ML310 schematics. The 5.0V PCI slots differ from the 3.3V slots. See the Important Instructions sheet

(PN 0402263) packaged with the ML310 kit before using Universal PCI add-in cards with the ML310 board.

36

www.xilinx.com

ML310 User Guide

 

1-800-255-7778

UG068 (v1.01) August 25, 2004

Image 36
Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProFoundation Features Foundation ISEDesign Entry Introduction to Virtex-II Pro, ISE, and EDKImplementation and Configuration SynthesisFoundation ISE Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareDDR Signaling DDR Memory ExpansionU37 DDRA2 DDRDQS02 DDRDQ31 Signaling Standards of RS-232 Serial Port Fpga UartIntroduction to Serial Ports RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACESystem ACE Jtag Configuration Interface Gpio LEDs and LCDParallel Cable IV Interface 8LEDs and LCD Connectivity UCF Signal Name Translator U37 J13 U35 Gpio LED InterfaceGpio LCD Interface U37 Name U36CPU Debug and CPU Trace CPU Debug DescriptionBuffer U33 J13 9Combined Trace/Debug Connector Pinout CPU Debug Connector Pinout PCI BusCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn ALi South Bridge Interface, M1535D+, U15 113.3V Primary PCI Bus Information Device VendorDevice Name Bus 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus SMBus17Type of Gpio Available on Header J5 ALi Gpio Types Number 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIIC/SMBus Signaling IIC/SMBus InterfaceIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPIPush Buttons, Switches, Front Panel Interface and Jumpers SPI AddressingPush Buttons System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 Jumpers Voltage JumperJ10 J11 Coupling ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorML310 PM Utility Pins Adapter Board PM ConnectorsContact Order ML310 PM User I/O Pins PM1 Power and GroundPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5