R
Chapter 2: ML310 Embedded Development Platform
Arbiter IP. Please see the EDK Processor IP Reference Guide for more information about the EDK IP mentioned in this section.
The FPGA is responsible generating the PCI RST signal as well as the PCI CLK signal. The FPGA fabric is used to generate six PCI Clocks that drive each of the PCI devices/slots shown in the Figure
The
♦Texas Instruments, TI2250,
♦Intel, GD82559, 10/100 PCI Ethernet NIC.
♦Ali, M1535D+, PCI South Bridge
In addition to the three fixed PCI devices, there are a total of four 33MHz/32 Bit PCI slots available for use. For more information on the PCI slot pinouts, refer to the PCI Local Bus Specification, Revision 2.2 and the ML310 schematics.
♦2 - 3.3V Keyed PCI Add In Card Slots (P5 and P3)
♦2 - 5.0V Keyed PCI Add In Card Slots (P6 and P4)
Note: The 5.0V PCI slots differ from the 3.3V slots. See the Important Instructions sheet (PN 0402263) packaged with the ML310 kit before using Universal PCI
Figure 2-11 shows the connectivity of the PCI bus and PCI devices. For more information on the PCI slot pinouts, refer to the PCI 2.2 Specification or review the ML310 schematics. The 5.0V PCI slots differ from the 3.3V slots. See the Important Instructions sheet
(PN 0402263) packaged with the ML310 kit before using Universal PCI add-in cards with the ML310 board.
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| UG068 (v1.01) August 25, 2004 |