Xilinx ML310 manual Pciinta Pciintb Pciintc

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Chapter 2: ML310 Embedded Development Platform

Table 2-10:PCI Controller Connections (Continued)

	UCF Signal Name	XC2VP30 Pin (U37)	Description

	PCI_INTA	L5

	PCI_INTB	N2

	PCI_INTC	M2	PCI Interrupt Signals

	PCI_INTD	R9
	PCI_INTD	R9

	PCI_INTE	P9

	PCI_INTF	M3

	PCI_REQ0_N	P1

	PCI_REQ1_N	N1

	PCI_REQ2_N	P7	PCI Request Signals

	PCI_REQ3_N	P8

	PCI_REQ4_N	N3

	PCI_GNT0_N	P2

	PCI_GNT1_N	P3

	PCI_GNT2_N	R7	PCI Grant Signals

	PCI_GNT3_N	R8

	PCI_GNT4_N	P4

	PCI_CBE[0]	J2

	PCI_CBE[1]	H2	PCI Byte Enable Signals

	PCI_CBE[2]	M7
	PCI_CBE[2]	M7

	PCI_CBE[3]	M8

	PCI_FRAME_N	K6

	PCI_IRDY_N	K1

	PCI_TRDY_N	J1

	PCI_STOP_N	M5

	PCI_DEVSEL_N	M6	PCI Control Signals

	PCI_PERR_N	J3

	PCI_SERR_N	J4

	PCI_LOCK	L2

	PCI_IDSEL	K2

	PCI_REQ64_N*	F8	# PM_IO_3V_1

	PCI_ACK64_N*	E8	# PM_IO_3V_2

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Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProDesign Entry Foundation FeaturesFoundation ISE Introduction to Virtex-II Pro, ISE, and EDKFoundation ISE Implementation and ConfigurationSynthesis Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareU37 DDR SignalingDDR Memory Expansion DDRA2 DDRDQS02 DDRDQ31 Introduction to Serial Ports Signaling Standards of RS-232Serial Port Fpga Uart RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACEParallel Cable IV Interface System ACE Jtag Configuration InterfaceGpio LEDs and LCD 8LEDs and LCD Connectivity Gpio LCD Interface UCF Signal Name Translator U37 J13 U35Gpio LED Interface U37 Name U36Buffer U33 J13 CPU Debug and CPU TraceCPU Debug Description 9Combined Trace/Debug Connector Pinout CPU Debug Connection to XC2VP30 CPU Debug Connector PinoutPCI Bus ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn Device Name Bus ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 17Type of Gpio Available on Header J5 ALi Gpio Types Number GPIO, connector J5System Management Bus SMBus 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIntroduction to IIC/SMBus IIC/SMBus SignalingIIC/SMBus Interface IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPIPush Buttons Push Buttons, Switches, Front Panel Interface and JumpersSPI Addressing System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 J10 J11 Coupling JumpersVoltage Jumper ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorContact Order ML310 PM Utility PinsAdapter Board PM Connectors PM2 Power and Ground ML310 PM User I/O PinsPM1 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5