Xilinx ML310 manual DDRDQ31

Board Hardware

Table 2-1:Connections from FPGA to DIMM Interface, P7

R

UCF Signal Name	XC2VP30 Pin	Schem Signal Name	DIMM
	(U37)		(P7)
ddr_dq[32]	N27	DDR_DQ31	133
ddr_dq[33]	P26	DDR_DQ30	131
ddr_dq[34]	R25	DDR_DQ29	127
ddr_dq[35]	R27	DDR_DQ28	126
ddr_dq[36]	N28	DDR_DQ27	40
ddr_dq[37]	P27	DDR_DQ26	39
ddr_dq[38]	R26	DDR_DQ25	35
ddr_dq[39]	R28	DDR_DQ24	33
ddr_dq[40]	K27	DDR_DQ23	123
ddr_dq[41]	L26	DDR_DQ22	121
ddr_dq[42]	M27	DDR_DQ21	117
ddr_dq[43]	N26	DDR_DQ20	114
ddr_dq[44]	K28	DDR_DQ19	31
ddr_dq[45]	L27	DDR_DQ18	28
ddr_dq[46]	M28	DDR_DQ17	24
ddr_dq[47]	N25	DDR_DQ16	23
ddr_dq[48]	K25	DDR_DQ15	110
ddr_dq[49]	K26	DDR_DQ14	109
ddr_dq[50]	J27	DDR_DQ13	106
ddr_dq[51]	J28	DDR_DQ12	105
ddr_dq[52]	M25	DDR_DQ11	20
ddr_dq[53]	M26	DDR_DQ10	19
ddr_dq[54]	J25	DDR_DQ09	13
ddr_dq[55]	J26	DDR_DQ08	12
ddr_dq[56]	H28	DDR_DQ07	99
ddr_dq[57]	G27	DDR_DQ06	98
ddr_dq[58]	F28	DDR_DQ05	95
ddr_dq[59]	E27	DDR_DQ04	94
ddr_dq[60]	H27	DDR_DQ03	8
ddr_dq[61]	G28	DDR_DQ02	6
ddr_dq[62]	F27	DDR_DQ01	4
ddr_dq[63]	E28	DDR_DQ00	2

The connections from the FPGA to the DDR DIMM support either a registered or an unbuffered DIMM. The only difference from a connectivity perspective is that the

ML310 User Guide	www.xilinx.com	25
UG068 (v1.01) August 25, 2004	1-800-255-7778