Xilinx ML310 manual System ACE Configuration Dipswitch, SW3, CPU Reset, SW2

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Chapter 2: ML310 Embedded Development Platform

CPU Reset, SW2

SW2 provides a way to manually reset the powerpc system implemented in the XC2VP30. The user is responsible for connecting this signal to the PPC405 system implemented in the FPGA fabric. The EDK kit provides IP to perform this task, please review the EDK Processor IP reference Guide for more details. When SW2 is actuated it drives the signal PB_FPGA_CPU_RESET low which causes the LTC1326 (U30) to generate a 100us active low pulse. The active low output of the LTC1326 pin E16 on the XC2VP30 (U38) device via signal FPGA_CPU_RESET_N. In addition to resetting the CPU, SW2 can also perform a System ACE CF reset as described in the above section. This can be accomplished by simply holding down the SW2 push button for longer than 2 seconds. This action performs a CPU reset followed by a System ACE CF reset. Please review the ML310 schematics and the LTC1236 data sheet found on the ML310 CDROM for more details.

The front panel interface header (J23) can also drive the PB_ FPGA_CPU_RESET signal. For more details on J23, please review section “Front Panel Interface Connector, J23”

System ACE Configuration Dipswitch, SW3

The System ACE configuration dipswitch is a three position dipswitch that controls the three configuration address pins on the System ACE CF controller. The three configuration address lines are; CFGADDR0, CFGADDR1 and CFGADDR2 and are marked as positions 1, 2 and 3 respectively on the dipswitch (SW3) plastic housing. Dipswitch SW3 is also marked with an "on" indicator that is etched onto the plastic housing of SW3 as well as an arrow head on the board silk-screen for SW3. When any of the three switches are moved to the "on" position then the associated CFGADDR bit is set to a logic zero. When any of the three switches are moved opposite of the "on" position then the associated CFGADDR bit is set to a logic one via a pull-up resistor.

Table 2-16depicts the SW3 dipswitch connections to the System ACE device. One side of the dipswitch is tied to pull-ups that are connected to each of the CFGADDR lines while the other side of the dipswitch is connected to ground. The configuration address lines are also connected to the Front Panel Interface, see “Front Panel Interface Connector, J23” for more details. This allows the user to manually select one of eight configurations stored on the CompactFlash that is connected to the System ACE device. Once the user makes a valid selection on SW3 the user can then depress push button SW1 to command the System ACE device to reset and configure the FPGA using the configuration selected by dipswitch SW3. Please review the System ACE CF data sheet which is available at http://www.xilinx.com or on the ML310 CDROM.

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ML310 User Guide

 

1-800-255-7778

UG068 (v1.01) August 25, 2004

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Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProDesign Entry Foundation FeaturesFoundation ISE Introduction to Virtex-II Pro, ISE, and EDKImplementation and Configuration SynthesisFoundation ISE Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareDDR Signaling DDR Memory ExpansionU37 DDRA2 DDRDQS02 DDRDQ31 Introduction to Serial Ports Signaling Standards of RS-232Serial Port Fpga Uart RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACESystem ACE Jtag Configuration Interface Gpio LEDs and LCDParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LCD Interface UCF Signal Name Translator U37 J13 U35Gpio LED Interface U37 Name U36CPU Debug and CPU Trace CPU Debug DescriptionBuffer U33 J13 9Combined Trace/Debug Connector Pinout CPU Debug Connector Pinout PCI BusCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn Device Name Bus ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus SMBus17Type of Gpio Available on Header J5 ALi Gpio Types Number 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIntroduction to IIC/SMBus IIC/SMBus SignalingIIC/SMBus Interface IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPIPush Buttons, Switches, Front Panel Interface and Jumpers SPI AddressingPush Buttons System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 Jumpers Voltage JumperJ10 J11 Coupling ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorML310 PM Utility Pins Adapter Board PM ConnectorsContact Order PM2 Power and Ground ML310 PM User I/O PinsPM1 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5
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