Xilinx manual ML310 Embedded Development Platform, Overview

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Chapter 2

ML310 Embedded Development Platform

Overview

The ML310 Embedded Development Platform offers designers a versatile Virtex-II Pro XC2VP30-FF896 based platform for rapid prototyping and system verification. In addition to the more than 30,000 logic cells, over 2,400 Kb of BRAM, dual PowerPC405 processors and RocketIO transceivers available in the FPGA, the ML310 provides an onboard Ethernet MAC/PHY, DDR memory, multiple PCI bus slots, and standard PC I/O ports within an ATX form factor board. An integrated System ACE CF controller is deployed to perform board bring-up and to load applications from the included 512 MB CompactFlash card.

The ML310 CDROM contains documentation and tutorials, along with reference designs and data sheets. The most recent ML310 material can be found on the Xilinx web site at http://www.xilinx.com/ml310.

The setup and quickstart documentation highlights the functionality of the ML310 using the applications shipped on the included CompactFlash card. The reference designs were produced using the Xilinx Embedded Development Kit (EDK), ISE and Answer Database solution records. Tutorials in coordination with Xilinx documentation for EDK, ISE, and the Answer Database, describe how the reference designs and applications were produced. These tutorials may be used to re-create the applications provided and also as a basis for the development of new designs. Xilinx EDK provides for the development of basic board specific systems beginning with Base System Builder (BSB) to highly customized systems leveraging the flexibility of Xilinx Platform Studio (XPS) and the EDK IP.

Documentation for Xilinx tools and solutions can be found at:

EDK: http://www.xilinx.com/edk

ISE: http://www.xilinx.com/ise

Answer Database: http://www.xilinx.com/support

An image of the ML310 board and its corresponding block diagram are shown in,

Figure 2-1andFigure 2-2respectively.

ML310 User Guide

www.xilinx.com

17

UG068 (v1.01) August 25, 2004

1-800-255-7778

 

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Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga Fabric Foundation ISE Foundation Features Design Entry Introduction to Virtex-II Pro, ISE, and EDKFoundation ISE Implementation and ConfigurationSynthesis Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryU37 DDR SignalingDDR Memory Expansion DDRA2 DDRDQS02 DDRDQ31 Serial Port Fpga Uart Signaling Standards of RS-232Introduction to Serial Ports RS-232 on the ML310Board Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30Parallel Cable IV Interface System ACE Jtag Configuration InterfaceGpio LEDs and LCD 8LEDs and LCD Connectivity Gpio LED Interface UCF Signal Name Translator U37 J13 U35Gpio LCD Interface U37 Name U36Buffer U33 J13 CPU Debug and CPU TraceCPU Debug Description 9Combined Trace/Debug Connector Pinout CPU Debug Connection to XC2VP30 CPU Debug Connector PinoutPCI Bus ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 113.3V Primary PCI Bus Information Device Vendor ALi South Bridge Interface, M1535D+, U15Device Name Bus 125.0V Secondary PCI Bus Information Device Name Vendor12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 17Type of Gpio Available on Header J5 ALi Gpio Types Number GPIO, connector J5System Management Bus SMBus AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus Interface IIC/SMBus SignalingIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingPush Buttons Push Buttons, Switches, Front Panel Interface and JumpersSPI Addressing CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 J10 J11 Coupling JumpersVoltage Jumper MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorContact Order ML310 PM Utility PinsAdapter Board PM Connectors PM1 Power and Ground ML310 PM User I/O PinsPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5