Xilinx ML310 manual AA5

Page 70

R

Chapter 2: ML310 Embedded Development Platform

	Table 2-32:	PM2 Pinout (Continued)

	PM2 Pin	FPGA Pin	Pin Description	ML310 Schematic Net	FPGA Bank
	PM2 Pin	FPGA Pin	Pin Description	ML310 Schematic Net	VCCO
					VCCO
	D14	AA5	IO_L44N_3	PM_IO_27	2.5V

	D15	AC4	IO_L43P_3	PM_IO_24	2.5V

	D16	AC3	IO_L43N_3	PM_IO_25	2.5V

	D17	AE4	IO_L33P_3	PM_IO_10	2.5V

	D18	AE3	IO_L33N_3	PM_IO_11	2.5V

	D19	AF4	IO_L34P_3	PM_IO_12	2.5V

	D20	AF3	IO_L34N_3	PM_IO_13	2.5V

	F1	AA1	IO_L51N_3	PM_IO_41	2.5V

	F2	AB1	IO_L51P_3	PM_IO_40	2.5V

	F3	U2	IO_L87N_3	PM_IO_65	2.5V

	F4	U3	IO_L87P_3	PM_IO_64	2.5V

	F5	Y2	IO_L54N_3	PM_IO_47	2.5V

	F6	AA2	IO_L54P_3	PM_IO_46	2.5V

	F7	Y4	IO_L49N_3	PM_IO_37	2.5V

	F8	Y5	IO_L49P_3	PM_IO_36	2.5V

	F9	NC	NC	NC	2.5V

	F10	AG15	IO_L74P_4	PM_CLK_BOT	2.5V

	F11	W8	IO_L47P_3	PM_IO_32	2.5V

	F12	W7	IO_L47N_3	PM_IO_33	2.5V

	F13	AB4	IO_L46P_3	PM_IO_30	2.5V

	F14	AB3	IO_L46N_3	PM_IO_31	2.5V

	F15	AE2	IO_L39P_3	PM_IO_18	2.5V

	F16	AE1	IO_L39N_3	PM_IO_19	2.5V

	F17	AH2	IO_L03P_3	PM_IO_2	2.5V

	F18	AH1	IO_L03N_3	PM_IO_3	2.5V

	F19	AD4	IO_L37P_3	PM_IO_16	2.5V

	F20	AD3	IO_L37N_3	PM_IO_17	2.5V

Notes:

1.LVDS pairs are shown shaded; all other signals are single-ended.

2.LVDS pairs can also be used as single-ended I/O at 2.5V

3.NC indicates a “no connect” signal.

70	www.xilinx.com	ML310 User Guide
	1-800-255-7778	UG068 (v1.01) August 25, 2004

Image 70

Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProDesign Entry Foundation FeaturesFoundation ISE Introduction to Virtex-II Pro, ISE, and EDKSynthesis Implementation and ConfigurationFoundation ISE Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareDDR Memory Expansion DDR SignalingU37 DDRA2 DDRDQS02 DDRDQ31 Introduction to Serial Ports Signaling Standards of RS-232Serial Port Fpga Uart RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACEGpio LEDs and LCD System ACE Jtag Configuration InterfaceParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LCD Interface UCF Signal Name Translator U37 J13 U35Gpio LED Interface U37 Name U36CPU Debug Description CPU Debug and CPU TraceBuffer U33 J13 9Combined Trace/Debug Connector Pinout PCI Bus CPU Debug Connector PinoutCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn Device Name Bus ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 System Management Bus SMBus GPIO, connector J517Type of Gpio Available on Header J5 ALi Gpio Types Number 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIntroduction to IIC/SMBus IIC/SMBus SignalingIIC/SMBus Interface IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPISPI Addressing Push Buttons, Switches, Front Panel Interface and JumpersPush Buttons System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 Voltage Jumper JumpersJ10 J11 Coupling ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorAdapter Board PM Connectors ML310 PM Utility PinsContact Order PM2 Power and Ground ML310 PM User I/O PinsPM1 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5